公开(公告)号：US07344973B2

公开(公告)日：2008-03-18

申请号：US11265683

申请日：2005-11-02

申请人： Kyung Ho Hwang ,  Won Mo Lee

发明人： Kyung Ho Hwang ,  Won Mo Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823475

摘要： Provided are a semiconductor device, adapted to be capable of fabricating the device having improved resistance characteristic by decreasing dishing of solid phase epitaxy (SPE) silicon during planarization in a landing plug forming process via use of SPE silicon, and a method of manufacturing the same.The method of manufacturing a semiconductor device in accordance with the present invention comprises, forming a plurality of gates on a semiconductor substrate; forming an interlayer dielectric film thereon, such that the gates are embedded; selectively etching the interlayer dielectric film to open a landing plug-forming region; depositing SPE silicon, such that the opened landing plug-forming region in the interlayer dielectric film is embedded; implanting boron ions into the SPE silicon; and annealing the resulting boron ion-implanted structure.

摘要翻译： 提供一种半导体器件，其适于能够通过使用SPE硅在着陆塞形成过程中的平坦化期间减少固相外延（SPE）硅的凹陷来制造具有改进的电阻特性的器件及其制造方法 。 根据本发明的制造半导体器件的方法包括：在半导体衬底上形成多个栅极; 在其上形成层间电介质膜，使得栅极被嵌入; 选择性地蚀刻层间电介质膜以打开着陆堵塞形成区域; 沉积SPE硅，使得层间绝缘膜中的开放的着色塞形成区被嵌入; 将硼离子注入SPE硅中; 并对所得的硼离子注入结构进行退火。

公开(公告)号：US08334207B2

公开(公告)日：2012-12-18

申请号：US12649559

申请日：2009-12-30

申请人： Ji-Min Lim ,  Kyung-ho Hwang

发明人： Ji-Min Lim ,  Kyung-ho Hwang

IPC分类号： H01L21/44

CPC分类号： H01L29/4236 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823456 ,  H01L27/105 ,  H01L27/1052

摘要： A method for fabricating a semiconductor device includes providing a substrate including cell regions and peripheral regions; selectively forming a gate conductive layer over the substrate in the peripheral regions, forming a sealing layer over the substrate with the gate conductive layer formed thereon, forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate, planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer, and forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer.

摘要翻译： 一种制造半导体器件的方法包括提供包括单元区域和外围区域的衬底; 在周边区域中的基板上选择性地形成栅极导电层，在其上形成有栅极导电层的基板上形成密封层，在密封层上形成绝缘层，以覆盖基板，栅极导电层形成在基板上 平坦化绝缘层以露出形成在栅极导电层上的密封层，并且在电池区域中形成多个插塞，多个插塞穿透绝缘层和密封层。

公开(公告)号：US20120153369A1

公开(公告)日：2012-06-21

申请号：US13182175

申请日：2011-07-13

申请人： Kyung Ho HWANG

发明人： Kyung Ho HWANG

IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L29/02 ,  H01L21/02

CPC分类号： H01L27/10894 ,  H01L27/10876

摘要： A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral circuit region, and an active region defined by a device isolation film, at least one dummy gate formed over the active region to expose a center part and both ends of the active region, a bit line contact plug formed between the dummy gates so as to be coupled to the center part of the active region, and a storage node contact plug that is spaced apart from the bit line contact plug by the dummy gate and is coupled to both ends of the active region. As a result, the problem that the storage node contact hole is not open in the semiconductor device can be solved, resulting in improved semiconductor device characteristics.

摘要翻译： 公开了半导体器件及其形成方法。 半导体器件包括包括单元区域和外围电路区域的半导体衬底以及由器件隔离膜限定的有源区，至少一个虚拟栅极，形成在有源区上方以暴露有源区的中心部分和两端 ，形成在虚拟栅极之间的位线接触插塞，以便耦合到有源区域的中心部分;以及存储节点接触插头，其通过虚拟栅极与位线接触插塞间隔开并耦合到两个 活动区域的末端。 结果，可以解决存储节点接触孔在半导体器件中不开放的问题，导致改进的半导体器件特性。