公开(公告)号：US08139592B2

公开(公告)日：2012-03-20

申请号：US12124524

申请日：2008-05-21

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Benjiman L. Goodman ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Benjiman L. Goodman ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： H04L12/28 ,  H04L12/56 ,  G06F13/00 ,  G06F13/28 ,  H04H20/71

CPC分类号： G06F12/0831 ,  G06F12/0897 ,  G06F12/1458

摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.

摘要翻译： 数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送 处理单位。 该通信包括具有请求的操作和表示对请求的系统响应的组合响应。 至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列 在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。 票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。

公开(公告)号：US07944932B2

公开(公告)日：2011-05-17

申请号：US12060751

申请日：2008-04-01

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke

IPC分类号： H04L12/28 ,  G06F15/173 ,  G06F15/76 ,  G06F15/00

CPC分类号： G06F15/16

摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts operations received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units.

摘要翻译： 数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。 多个处理单元中的每一个包括互连逻辑，耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个处理单元接收的操作广播到多个处理单元中的一个或多个 处理单位。

公开(公告)号：US07577797B2

公开(公告)日：2009-08-18

申请号：US11388016

申请日：2006-03-23

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first processing unit having a first cache memory. The second coherency domain includes a second processing unit having a second cache memory. In the first cache memory, a coherency state field associated with a storage location and an address tag is set to a first coherency state. In response to snooping an exclusive access request specifying a target address matching the address tag, the first cache memory provides a first partial response to the exclusive access request based at least in part upon the first coherency state. In response to snooping the exclusive access request, the memory controller determines whether it is responsible for the target address and provides a second partial response to the exclusive access request based at least in part upon an outcome of the determination. At least the first and second partial responses are accumulated to obtain a combined response for the exclusive access request. The combined response includes an indication of whether or not a highest point of coherency and a memory controller of a home system memory for the target address reside within a same coherency domain. The first cache memory updates the coherency state field from the first coherency state to a second coherency state in response to the indication in the combined response.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 第一相干域包括用于系统存储器的系统存储器控制器和具有第一高速缓冲存储器的第一处理单元。 第二相关域包括具有第二高速缓冲存储器的第二处理单元。 在第一缓存存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为第一相关性状态。 响应于窥探专用访问请求，指定与地址标签匹配的目标地址，第一高速缓存存储器至少部分地基于第一相关性状态向独占访问请求提供第一部分响应。 响应于窥探专用访问请求，存储器控制器至少部分地基于确定的结果来确定它是否对目标地址负责并且向独占访问请求提供第二部分响应。 至少第一和第二部分响应被累积以获得专用访问请求的组合响应。 组合响应包括关于目标地址的家庭系统存储器的最高点的一致性和存储器控制器是否位于相同的一致性域内的指示。 响应于组合响应中的指示，第一缓存存储器将相关性状态字段从第一相关性状态更新为第二相关性状态。

公开(公告)号：US07467262B2

公开(公告)日：2008-12-16

申请号：US11136642

申请日：2005-05-24

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： In response to execution of program code, a control register within scrubbing logic in a local coherency domain is initialized with at least a target address of a target memory block. In response to the initialization, the scrubbing logic issues to at least one cache hierarchy in a remote coherency domain a domain indication scrubbing request targeting a target memory block that may be cached by the at least one cache hierarchy. In response to receipt of a coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.

摘要翻译： 响应于程序代码的执行，用至少目标存储器块的目标地址初始化局部一致性域内的擦除逻辑中的控制寄存器。 响应于初始化，擦除逻辑向远程一致性域中的至少一个高速缓存层级发出针对可由所述至少一个高速缓存层级缓存的目标存储器块的域指示擦除请求。 响应于接收到指示目标存储器块未被缓存在远程一致性域中的一致性响应，本地一致性域中的域指示被更新以指示目标存储器块被缓存，如果完全只在 局部一致性域。

公开(公告)号：US07890704B2

公开(公告)日：2011-02-15

申请号：US11612568

申请日：2006-12-19

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Pak-Kin Mak ,  William J. Starke

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Pak-Kin Mak ,  William J. Starke

IPC分类号： G06F12/08

CPC分类号： G06F12/0831

摘要： A system and method for implementing an enhanced hover state with active prefetches. According to a preferred embodiment of the present invention, a snooper in a processing unit receives a system-wide update complete operation indicating a completion of a storage-modifying operation targeting a particular address, where the storage-modifying operation results in a modified first cache line in a first cache memory. The snooper determines if a second cache memory held a second cache line associated with the particular address prior to receiving the system-wide update complete operation. If so, the snooper issues a prefetch request for a copy of the modified first cache line to replace the second cache line in the second cache memory. The snooper updates the second cache memory with a copy of the modified first cache line.

摘要翻译： 一种用于实现具有活动预取的增强悬停状态的系统和方法。 根据本发明的优选实施例，处理单元中的窥探者接收指示完成针对特定地址的存储修改操作的全系统更新完成操作，其中存储修改操作导致修改的第一高速缓存 在第一个缓存内存中。 在接收全系统更新完成操作之前，窥探者确定第二高速缓冲存储器是否保持与特定地址相关联的第二高速缓存行。 如果是这样，侦听器发出修改的第一高速缓存行的副本的预取请求，以替换第二高速缓存存储器中的第二高速缓存行。 窥探者使用修改的第一个高速缓存行的副本更新第二个高速缓存。

公开(公告)号：US07475195B2

公开(公告)日：2009-01-06

申请号：US11136651

申请日：2005-05-24

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0822

摘要： Scrubbing logic in a local coherency domain issues to at least one cache hierarchy in a remote coherency domain a domain reset request that forces invalidation of any cached copy of a target memory block then held in said remote coherency domain. A coherency response to said domain reset request is received. In response to said coherency response indicating that said target memory block is not cached in said remote coherency domain, a domain indication of said local coherency domain is updated to indicate that said target memory block is cached, if at all, only within said local coherency domain.

摘要翻译： 本地一致性域中的擦除逻辑向远程一致性域中的至少一个高速缓存层次结构发出一个域重置请求，该请求强制所保存在所述远程一致性域中的目标存储器块的任何高速缓存副本的无效。 接收到对所述域重置请求的一致性响应。 响应于所述相关性响应指示所述目标存储器块未被高速缓存在所述远程一致性域中，所述本地一致性域的域指示被更新以指示所述目标存储器块被缓存，如果完全只在所述局部一致性内 域。

公开(公告)号：US20080222648A1

公开(公告)日：2008-09-11

申请号：US12124524

申请日：2008-05-21

申请人： LEO J. CLARK ,  James S. Fields ,  Benjiman L. Goodman ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： LEO J. CLARK ,  James S. Fields ,  Benjiman L. Goodman ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F9/46

CPC分类号： G06F12/0831 ,  G06F12/0897 ,  G06F12/1458

摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.

摘要翻译： 数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送 处理单位。 该通信包括具有请求的操作和表示对请求的系统响应的组合响应。 至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列 在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。 票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。

公开(公告)号：US20080181244A1

公开(公告)日：2008-07-31

申请号：US12060751

申请日：2008-04-01

申请人： LEO J. CLARK ,  James S. Fields ,  Guy L. Guthrie ,  William J. Starke

发明人： LEO J. CLARK ,  James S. Fields ,  Guy L. Guthrie ,  William J. Starke

IPC分类号： H04L12/56

CPC分类号： G06F15/16

摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts operations received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units.

摘要翻译： 数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。 多个处理单元中的每一个包括互连逻辑，耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个处理单元接收的操作广播到多个处理单元中的一个或多个 处理单位。

公开(公告)号：US20080147991A1

公开(公告)日：2008-06-19

申请号：US11612568

申请日：2006-12-19

申请人： Leo J. Clark ,  James S. Fields ,  Pak-Kin Mak ,  William J. Starke

发明人： Leo J. Clark ,  James S. Fields ,  Pak-Kin Mak ,  William J. Starke

IPC分类号： G06F12/08

CPC分类号： G06F12/0831

摘要： A system and method for implementing an enhanced hover state with active prefetches. According to a preferred embodiment of the present invention, a snooper in a processing unit receives a system-wide update complete operation indicating a completion of a storage-modifying operation targeting a particular address, where the storage-modifying operation results in a modified first cache line in a first cache memory. The snooper determines if a second cache memory held a second cache line associated with the particular address prior to receiving the system-wide update complete operation. If so, the snooper issues a prefetch request for a copy of the modified first cache line to replace the second cache line in the second cache memory. The snooper updates the second cache memory with a copy of the modified first cache line.

摘要翻译： 一种用于实现具有活动预取的增强悬停状态的系统和方法。 根据本发明的优选实施例，处理单元中的窥探者接收指示完成针对特定地址的存储修改操作的全系统更新完成操作，其中存储修改操作导致修改的第一高速缓存 在第一个缓存内存中。 在接收全系统更新完成操作之前，窥探者确定第二高速缓冲存储器是否保持与特定地址相关联的第二高速缓存行。 如果是这样，侦听器发出修改的第一高速缓存行的副本的预取请求，以替换第二高速缓存存储器中的第二高速缓存行。 窥探者使用修改的第一个高速缓存行的副本更新第二个高速缓存。

公开(公告)号：US07254694B2

公开(公告)日：2007-08-07

申请号：US11055297

申请日：2005-02-10

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F15/16

CPC分类号： G06F13/385 ,  G06F9/546

摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response. The interconnect logic accumulates partial responses of processing units by reference to the partial response field to obtain an accumulated partial response, and when the plurality of flags indicate that all processing units from which partial responses are expected have returned a partial response, outputs the accumulated partial response.

摘要翻译： 数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。 多个处理单元中的每一个包括互连逻辑，其耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个的接收的请求广播到多个处理单元中的一个或多个 处理单位。 互连逻辑包括部分响应数据结构，其包括多个条目，每个条目将部分响应字段与分别与包含窥探者的每个处理单元相关联的多个标志相关联，该处理单元将从该处理单元接收部分响应。 互连逻辑通过参考部分响应字段积累处理单元的部分响应以获得累积的部分响应，并且当多个标志指示预期部分响应的所有处理单元已经返回部分响应时，输出累积的部分响应 响应。