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1.发明授权Data processing system and method for predictively selecting a scope of broadcast of an operation 有权用于预测性地选择操作的广播范围的数据处理系统和方法公开(公告)号：US08140770B2
公开(公告)日：2012-03-20
申请号：US11054886
申请日：2005-02-10
IPC分类号： G06F12/00
CPC分类号： G06F12/0844 , G06F12/0817 , G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains coupled for communication. The first and second coherency domains each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains based, at least in part, upon a type of the operation. The master then performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.
摘要翻译： 高速缓存一致数据处理系统至少包括耦合用于通信的第一和第二相干域。 第一和第二相关域各自包括第一和第二高速缓存存储器中的相应一个。 第一相关域中的主机至少部分地基于类型，从包括第一相关域的第一范围和包括第一和第二相干域两者的第二范围中选择操作的初始广播的范围 的操作。 然后，主机使用所选择的范围在高速缓存相干数据处理系统内执行操作的初始广播。
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2.发明授权Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule 失效数据处理系统，处理器和数据处理方法，其中本地存储器访问请求以固定的时间表被服务公开(公告)号：US07447844B2
公开(公告)日：2008-11-04
申请号：US11457322
申请日：2006-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F12/0817 , G06F12/0897
摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
摘要翻译： 处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录。 缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑 其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。 调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。
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3.发明申请Data Processing System, Processor and Method of Data Processing in which Local Memory Access Requests are Serviced by State Machines with Differing Functionality 失效数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务公开(公告)号：US20080016279A1
公开(公告)日：2008-01-17
申请号：US11457333
申请日：2006-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译： 数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。 多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求， 它能够维修。
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4.发明授权Interlock for controlling processor ownership of pipelined data for a store in cache 失效用于控制缓存中存储的流水线数据的处理器所有权的联锁
公开(公告)号：US5490261A
公开(公告)日：1996-02-06
申请号：US680176
申请日：1991-04-03
申请人： Bradford M. Bean , Anne E. Bierce , Neal T. Christensen , Leo J. Clark , Steven T. Comfort , Christine C. Jones , Pak-Kin Mak
发明人： Bradford M. Bean , Anne E. Bierce , Neal T. Christensen , Leo J. Clark , Steven T. Comfort , Christine C. Jones , Pak-Kin Mak
CPC分类号： G06F12/0811
摘要： Insures data integrity in process ownership indications by providing an ownership interlock on the data units in a pipeline to a store-in type of cache. An ownership interlock prevents any processor ownership change to occur (i.e. exclusive or readonly ownership) for a cache data unit until all outstanding stores have been made in the cache data unit, after which the ownership may be changed. An ownership change may be signalled by a cross-invalidate (XI) signal to a processor. Outstanding stores are received by the pipeline after the stores are completed by a processor, and the outstanding stores output from the pipeline into a store-in cache. A continuous flow of stores is enabled into and out of the pipeline to expedite a change of ownership requested of a data unit in the cache. The continuous flow avoids having to stop a processor from putting stores into the pipeline and avoids forcing all outstanding stores out of the pipeline into the cache before indicating a change of processor ownership.
摘要翻译： 通过在流水线中的数据单元上提供所有权互锁到存储型缓存来保护进程所有权指示中的数据完整性。 所有权互锁防止对高速缓存数据单元发生任何处理器所有权改变（即，独占或只读所有权），直到所有未完成的存储已经在高速缓存数据单元中进行，之后可以改变所有权。 所有权变更可以通过交叉无效（XI）信号发送给处理器。 在存储由处理器完成之后，流水线接收到未完成的存储，并且从流水线输出的未完成存储到存储缓存中。 连续的商店流程被启用进出管道，以加快对高速缓存中数据单元所需的所有权的更改。 连续流程避免了停止处理器将存储放入流水线中，并避免在指示处理器所有权的更改之前将所有未完成的存储从管道中强制进入高速缓存。
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公开(公告)号：US08205024B2
公开(公告)日：2012-06-19
申请号：US11560619
申请日：2006-11-16
CPC分类号： G06F15/173
摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.
摘要翻译： 在数据处理系统中，多个代理之间进行通信。 每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。 观察到请求的延迟和多个代理之间的组合响应。 通过参考所观察到的延迟，多个代理中的每个被配置有保护窗口扩展的相应持续时间。 每个保护窗口扩展是在绞盘期间接收到组合响应之后的周期，多个代理之一相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。 多个代理根据配置使用保护窗口扩展，并且至少两个代理具有不同持续时间的保护窗口扩展。
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6.发明授权Data processing system, cache system and method for passively scrubbing a domain indication 失效数据处理系统，缓存系统和被动清理域指示的方法公开(公告)号：US07478201B2
公开(公告)日：2009-01-13
申请号：US11136652
申请日：2005-05-24
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Scrubbing logic in a local coherency domain issues a domain query request to at least one cache hierarchy in a remote coherency domain. The domain query request is a non-destructive probe of a coherency state associated with a target memory block by the at least one cache hierarchy. A coherency response to the domain query request is received. In response to the coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.
摘要翻译： 本地一致性域中的擦除逻辑向远程一致性域中的至少一个缓存层次结构发出域查询请求。 域查询请求是由至少一个高速缓存层次结构与目标存储器块相关联的一致性状态的非破坏性探测。 接收到域查询请求的一致性响应。 响应于指示目标存储器块未被缓存在远程一致性域中的相关性响应，本地一致性域中的域指示被更新以指示目标存储器块被缓存，如果完全只在本地一致性内 域。
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7.发明授权Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality 失效数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务公开(公告)号：US07447845B2
公开(公告)日：2008-11-04
申请号：US11457333
申请日：2006-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译： 数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。 多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求， 它能够维修。
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8.发明申请DATA PROCESSING SYSTEM, METHOD AND INTERCONNECT FABRIC SUPPORTING DESTINATION DATA TAGGING 失效数据处理系统，方法和互连织物支持目的地数据标签公开(公告)号：US20080209135A1
公开(公告)日：2008-08-28
申请号：US12117539
申请日：2008-05-08
IPC分类号： G06F12/00
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.
摘要翻译： 数据处理系统包括多个通信链路和包括本地主处理单元的多个处理单元。 本地主处理单元包括将处理单元耦合到多个通信链路中的一个或多个以及耦合到互连逻辑的始发主机的互连逻辑。 始发主机通过在一个或多个通信链路中的至少一个发出写入请求来发起操作，从数据处理系统中的窥探者接收标识到窥探者的路由的目的地标签，并且响应于接收到 组合响应和目的地标签，发起包括数据有效载荷和标识目的地标签内提供的路由的数据标签的数据传输。
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9.发明申请Data Processing System, Processor and Method of Data Processing in which Local Memory Access Requests are Serviced on a Fixed Schedule 失效数据处理系统，处理器和数据处理方法，其中本地存储器访问请求在固定时间表上服务公开(公告)号：US20080016278A1
公开(公告)日：2008-01-17
申请号：US11457322
申请日：2006-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F12/0817 , G06F12/0897
摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
摘要翻译： 处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录。 缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑 其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。 调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。
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10.发明授权Data processing system, method and interconnect fabric having a flow governor 有权具有流量调节器的数据处理系统，方法和互连结构公开(公告)号：US08254411B2
公开(公告)日：2012-08-28
申请号：US11055399
申请日：2005-02-10
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke
IPC分类号： H04J3/16 , H04J3/22 , G06F13/00 , G06F15/173
CPC分类号： H04L47/722 , H04L47/70 , H04L49/109
摘要： A data processing system includes a plurality of local hubs each coupled to a remote hub by a respective one a plurality of point-to-point communication links. Each of the plurality of local hubs queues requests for access to memory blocks for transmission on a respective one of the point-to-point communication links to a shared resource in the remote hub. Each of the plurality of local hubs transmits requests to the remote hub utilizing only a fractional portion of a bandwidth of its respective point-to-point communication link. The fractional portion that is utilized is determined by an allocation policy based at least in part upon a number of the plurality of local hubs and a number of processing units represented by each of the plurality of local hubs. The allocation policy prevents overruns of the shared resource.
摘要翻译： 数据处理系统包括多个本地集线器，每个集线器通过相应的一个多个点对点通信链路耦合到远程集线器。 多个本地集线器中的每一个排队对存储器块进行访问的请求，用于在到远程集线器中的共享资源的点对点通信链路中的相应一个上传输。 多个本地集线器中的每一个仅利用其相应点对点通信链路的带宽的小数部分向远程集线器发送请求。 所使用的分数部分由至少部分地基于多个本地集线器的数量和由多个本地集线器中的每一个表示的多个处理单元的分配策略确定。 分配策略可以防止超出共享资源。
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