公开(公告)号：US07362089B2

公开(公告)日：2008-04-22

申请号：US10912848

申请日：2004-08-06

申请人： Eric Barr Kushnick ,  Yasuo Furukawa ,  Lawrence Kraus ,  James Getchell

发明人： Eric Barr Kushnick ,  Yasuo Furukawa ,  Lawrence Kraus ,  James Getchell

IPC分类号： G01R31/28

CPC分类号： G01R31/31907

摘要： A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.

公开(公告)号：US5930814A

公开(公告)日：1999-07-27

申请号：US697968

申请日：1996-09-03

申请人： Yervant David Lepejian ,  Hrant Marandjian ,  Hovhannes Ghukasyan ,  Lawrence Kraus

发明人： Yervant David Lepejian ,  Hrant Marandjian ,  Hovhannes Ghukasyan ,  Lawrence Kraus

IPC分类号： G11C29/18 ,  G11C29/26 ,  G06F12/00 ,  G11C29/00

CPC分类号： G11C29/18 ,  G11C29/26

摘要： A method and circuit are provided for generating a minimum-sized address filter to detect when the address space of an embedded memory having a smaller address space than another larger embedded memory is being exceeded. The method includes decomposing a maximum address into alternating sequences of consecutive binary ones (1's) and zeros (0's), discarding a final sequence if it contains binary 1's, and generating a filter circuit from a filter function formed from the alternating sequences of consecutive binary 1's and 0's. A built-in self test (BIST) circuit incorporating the address filter provides the ability to test a plurality of embedded memories at full speed in parallel. A computer system including a computer program for generating the filter circuit may also be provided.

摘要翻译： 提供了一种方法和电路，用于产生最小尺寸的地址过滤器，以便检测何时超出了具有比另一较大嵌入式存储器更小的地址空间的嵌入式存储器的地址空间。 该方法包括将最大地址分解为连续二进制（1）和零（0）的交替序列，如果包含二进制1则丢弃最终序列，并从由连续二进制的交替序列形成的滤波器函数生成滤波器电路 1和0。 结合地址滤波器的内置自测（BIST）电路提供了以全速并行测试多个嵌入式存储器的能力。 还可以提供包括用于生成滤波器电路的计算机程序的计算机系统。

公开(公告)号：US06587979B1

公开(公告)日：2003-07-01

申请号：US09494824

申请日：2000-01-31

申请人： Lawrence Kraus ,  Ivan-Pierre Batinic ,  Marc P. Loranger ,  Hiralal Ranga

发明人： Lawrence Kraus ,  Ivan-Pierre Batinic ,  Marc P. Loranger ,  Hiralal Ranga

IPC分类号： G11C2900

CPC分类号： G11C29/48 ,  G11C29/46 ,  G11C2029/1206 ,  G11C2207/104

摘要： A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.

摘要翻译： 灵活的内置自检（BIST）电路被集成到集成电路（IC）中，用于测试嵌入在集成电路中的一个或随机存取存储器或其他存储器，而不管存储器的数量，尺寸或测试要求如何。 来自控制器的输入数据可以方便地在IC内部和外部的组件之间分配，向BIST电路提供数据，指示要测试的嵌入式存储器的大小，并从多种BIST操作模式中进行选择。

公开(公告)号：US6011748A

公开(公告)日：2000-01-04

申请号：US917013

申请日：1997-08-21

申请人： Yervant David Lepejian ,  Hovhannes Ghukasyan ,  Lawrence Kraus

发明人： Yervant David Lepejian ,  Hovhannes Ghukasyan ,  Lawrence Kraus

IPC分类号： G11C29/34 ,  G11C7/00

CPC分类号： G11C29/34

摘要： A BIST function is provided in which both the row address and the column address of a memory to be tested may be selected independently. The present invention provides flexibility in selecting addresses to be tested, improves transition time between rows, and allows determination of which memory address passes or fails the test.

摘要翻译： 提供BIST功能，其中可以独立地选择待测试的存储器的行地址和列地址。 本发明提供了选择要测试的地址的灵活性，改善了行之间的转换时间，并且允许确定哪个存储器地址通过或测试失败。

公开(公告)号：US5974579A

公开(公告)日：1999-10-26

申请号：US707062

申请日：1996-09-03

申请人： Yervant David Lepejian ,  Hrant Marandjian ,  Hovhannes Ghukasyan ,  John Caywood ,  Lawrence Kraus

发明人： Yervant David Lepejian ,  Hrant Marandjian ,  Hovhannes Ghukasyan ,  John Caywood ,  Lawrence Kraus

IPC分类号： G11C29/20 ,  G11C29/28 ,  G01R31/28

CPC分类号： G11C29/20 ,  G11C29/28

摘要： A built-in self test (BIST) circuit for an integrated circuit tests one or more embedded memories by writing data to each memory address, reading it back out, and then comparing the input and output data to see if they match. The BIST circuit includes one or more data generators for supplying a sequence of data to be written to the various addresses of each memory and one or more identical address generators, each for supplying addresses to a separate embedded memory during read and write operations. Though the memories may have differently sized address spaces, all address generators generate a similar address sequence having a range of address values as large or larger than the address space of the largest memory. During each memory write cycle, a separate filter checks the address output of each address generator to determine whether the address is within the address space of the corresponding memory. If so, the BIST circuit writes the current data output of a data generator to that address of the memory. If not, the BIST circuit ignores the current address and data outputs of the address and data generators and repeats the write operation it performed during a next preceding memory write cycle, writing the same data to the same valid memory address. The BIST circuit makes a similar address substitution during write operation. This allows the BIST circuit to use identical address generators for all memories regardless of the size of the memory being tested.

摘要翻译： 用于集成电路的内置自测（BIST）电路通过将数据写入每个存储器地址进行一个或多个嵌入式存储器的测试，将其读出，然后比较输入和输出数据，看它们是否匹配。 BIST电路包括一个或多个数据生成器，用于提供要写入每个存储器的各个地址的数据序列以及一个或多个相同的地址生成器，每个地址生成器用于在读取和写入操作期间向单独的嵌入式存储器提供地址。 虽然存储器可能具有不同大小的地址空间，但是所有地址生成器生成类似的地址序列，其地址值的范围大于或大于最大存储器的地址空间。 在每个存储器写入周期期间，单独的滤波器检查每个地址发生器的地址输出，以确定地址是否在相应存储器的地址空间内。 如果是这样，BIST电路将数据发生器的当前数据输出写入存储器的地址。 如果不是，则BIST电路忽略地址和数据发生器的当前地址和数据输出，并重复在下一个前一个存储器写周期期间执行的写操作，将相同的数据写入相同的有效存储器地址。 BIST电路在写操作期间进行类似的地址替换。 这允许BIST电路为所有存储器使用相同的地址生成器，而不管正在测试的存储器的大小。