公开(公告)号：US20070281406A1

公开(公告)日：2007-12-06

申请号：US11445215

申请日：2006-06-02

申请人： Li-Shu Chen

发明人： Li-Shu Chen

IPC分类号： H01L21/337

CPC分类号： H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7722

摘要： A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor. A greater separation between a source and gate is obtained by placing a spacer layer on the sidewalls of the pillars, either before or after formation of the skirt

摘要翻译： 制造用于静态感应晶体管的半导体结构的方法。 三层SiC材料在基材上，顶层被厚氧化物覆盖。 具有多个条带的掩模沉积在氧化物的顶部以保护其下面的区域，并且蚀刻去除氧化物，第三层和少量的第二层，留下多个柱。 氧化步骤在每个柱的基部周围生长氧化物裙部，并且消耗氧化物下方的第三层的边缘部分以形成源。 离子注入在裙边之间形成门区。 同时，形成多个保护环。 去除所有氧化物导致可以使源极，栅极和漏极连接形成静电感应晶体管的半导体结构。 源极和栅极之间的更大间隔是通过在衬垫的侧壁上放置间隔层，或者在形成裙部之前或之后

公开(公告)号：US06939784B2

公开(公告)日：2005-09-06

申请号：US10820761

申请日：2004-04-09

申请人： Li-Shu Chen ,  Philip C. Smith ,  Thomas J. Moloney ,  Howard Fudem

发明人： Li-Shu Chen ,  Philip C. Smith ,  Thomas J. Moloney ,  Howard Fudem

IPC分类号： B81B7/00 ,  H01L21/50 ,  H01L23/10 ,  H01L21/30 ,  H01L21/48

CPC分类号： H01L23/10 ,  B81B2201/018 ,  B81B2207/097 ,  B81C1/00301 ,  B81C2203/0118 ,  H01L21/50 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/3011 ,  H01L2924/00

摘要： A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

摘要翻译： 多个电子电路和相关联的信号线位于基底晶片上的相应位置。 安装在基底晶片上方的覆盖晶片包括相应的相似数量的位置，每个位置包括一个或多个空腔以容纳电子电路和相关联的信号线。 覆盖晶片包括用于与信号线进行电连接的多个通孔。 多层金属装置密封每个位置的周边以及密封每个通孔的底部。 然后可以将接合的基底和覆盖晶片切割成单独的管芯封装。

公开(公告)号：US5851852A

公开(公告)日：1998-12-22

申请号：US600777

申请日：1996-02-13

申请人： John A. Ostop ,  Li-Shu Chen

发明人： John A. Ostop ,  Li-Shu Chen

IPC分类号： H01L21/52 ,  H01L21/60 ,  H01L21/58

CPC分类号： H01L24/83 ,  H01L24/29 ,  H01L2224/29111 ,  H01L2224/29155 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10272

摘要： A die attach procedure for SiC uses the scrubbing technique to bond a SiC die to a package. A first layer is formed on the SiC die. This first layer, preferably of nickel, bonds to the SiC die. A second layer, preferably amorphous silicon, is then formed on the first layer. The second layer bonds to the first layer, and forms a eutectic with the material, usually gold, plating the package when the SiC die is scrubbed onto the package.

摘要翻译： SiC的芯片附着程序使用擦洗技术将SiC晶片粘合到封装上。 在SiC芯片上形成第一层。 该第一层，优选镍，与SiC晶粒结合。 然后在第一层上形成第二层，优选非晶硅。 第二层结合到第一层，并且当SiC芯片被擦洗到封装上时，与材料（通常为金）形成与共晶体的电镀。

公开(公告)号：US07547586B2

公开(公告)日：2009-06-16

申请号：US11445215

申请日：2006-06-02

申请人： Li-Shu Chen

发明人： Li-Shu Chen

IPC分类号： H01L21/332

CPC分类号： H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7722

摘要： A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor. A greater separation between a source and gate is obtained by placing a spacer layer on the sidewalls of the pillars, either before or after formation of the skirt.

摘要翻译： 制造用于静态感应晶体管的半导体结构的方法。 三层SiC材料在基材上，顶层被厚氧化物覆盖。 具有多个条带的掩模沉积在氧化物的顶部以保护其下面的区域，并且蚀刻去除氧化物，第三层和少量的第二层，留下多个柱。 氧化步骤在每个柱的基部周围生长氧化物裙部，并且消耗氧化物下方的第三层的边缘部分以形成源。 离子注入在裙边之间形成门区。 同时，形成多个保护环。 去除所有氧化物导致可以使源极，栅极和漏极连接形成静电感应晶体管的半导体结构。 通过在裙部的形成之前或之后将间隔层放置在柱的侧壁上来获得源极和栅极之间的更大间隔。

公开(公告)号：US5807773A

公开(公告)日：1998-09-15

申请号：US688587

申请日：1996-07-30

申请人： Li-Shu Chen ,  Rowland C. Clarke ,  Richard R. Siergiej

发明人： Li-Shu Chen ,  Rowland C. Clarke ,  Richard R. Siergiej

IPC分类号： H01L21/04 ,  H01L21/337

CPC分类号： H01L29/66068 ,  Y10S438/931

摘要： A method of aligning a gate and a source of a silicon carbide static induction transistor comprising the steps of depositing an oxide layer over the transistor, forming oxide spacers from the oxide layer where the oxide spacers are adjacent the source, depositing a metal layer over the transistor and removing the oxide spacers so that the resulting gates are accurately aligned with the source.

摘要翻译： 一种对准碳化硅静电感应晶体管的栅极和源极的方法，包括以下步骤：在所述晶体管上沉积氧化物层，从所述氧化物层形成氧化物间隔物，其中所述氧化物间隔物邻近所述源，在所述氧化物层上沉积金属层 去除氧化物间隔物，使得所得到的栅极与源极准确对准。