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    Multiprocessor with split transaction bus architecture for sending retry direction to other bus module upon a match of subsequent address bus cycles to content of cache tag
    11.
    发明授权
    Multiprocessor with split transaction bus architecture for sending retry direction to other bus module upon a match of subsequent address bus cycles to content of cache tag 失效
    具有分割事务总线架构的多处理器，用于在将后续地址总线周期匹配到缓存标签的内容时向其他总线模块发送重试方向

    公开(公告)号：US5732244A

    公开(公告)日：1998-03-24

    申请号：US505987

    申请日：1995-07-24

    申请人： Manoj Gujral

    发明人： Manoj Gujral

    IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F15/16

    CPC分类号： G06F12/0831 ,  G06F12/0833

    摘要： A method of arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, including bus modules operating with an address phase and a cycle phase, and arranged for access by a prescribed resource stage, to facilitate "RETRY", this method including; providing a Cache Tag and Address Compare, arranging the system so that a first bus module stores the address for the Resource stage in the Cycle Tag; and comparing subsequent address bus cycles to the contents of the Cache Tag so that, given a "match", a "RETRY" direction is responsively sent to any other bus module that requests access.

    摘要翻译： 一种布置和操作具有“分割事务总线”架构的多处理器计算机服务器系统的方法，包括以地址相位和周期阶段运行的总线模块，并且被布置为通过规定的资源阶段进行访问，以便于“重试”，这 方法包括 提供缓存标签和地址比较，安排系统，使得第一总线模块将资源阶段的地址存储在周期标签中; 并且将后续地址总线周期与缓存标签的内容进行比较，使得在给定“匹配”的情况下，“重试”方向被响应地发送到请求访问的任何其他总线模块。

    Avoiding instability
    12.
    发明授权
    Avoiding instability 失效
    避免不稳定

    公开(公告)号：US5638015A

    公开(公告)日：1997-06-10

    申请号：US493383

    申请日：1995-06-21

    申请人： Manoj Gujral ,  Greggory D. Donley ,  Paul N. Israel

    发明人： Manoj Gujral ,  Greggory D. Donley ,  Paul N. Israel

    IPC分类号： G06F1/04 ,  G11C7/22 ,  G11C8/06 ,  H03K3/037 ,  H03K5/00 ,  H03K5/13

    CPC分类号： H03K3/0375 ,  G06F1/04 ,  G11C7/22 ,  G11C8/06

    摘要： Described are techniques to stabilize storage devices receiving signals from plural asynchronous docks, especially to avoid "metastability", in particular, a multi-dock pulse synchronizer circuit with an IN-section for receiving and storing prescribed impulses and input cock signals, and for responsively outputting intermediate signals: and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals which avoid metastability.

    摘要翻译： 描述了用于稳定从多个异步基站接收信号的存储设备的技术，特别是为了避免“亚稳态”，特别是具有用于接收和存储规定的脉冲和输入旋转信号的IN部分的多基准脉冲同步器电路，并且用于响应地 输出中间信号和OUT部分，用于接收和存储与某些输出时钟信号同步的中间脉冲，并处理它们以产生避免亚稳态的某些输出信号。