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公开(公告)号:US08645762B2
公开(公告)日:2014-02-04
申请号:US12963086
申请日:2010-12-08
申请人: Greggory D. Donley
发明人: Greggory D. Donley
IPC分类号: G06F11/00
CPC分类号: G06F11/079 , G06F11/0724
摘要: A method and apparatus for retrieving a state of a processor at a time at which failure is detected. More specifically, the detection of one or more protocol errors results in the halting of operations of one or more system elements, and the retrieving of the state of the processor at the time of the failure.
摘要翻译: 一种用于在检测到故障的时间检索处理器的状态的方法和装置。 更具体地,检测到一个或多个协议错误导致停止一个或多个系统元件的操作,以及在故障时检索处理器的状态。
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公开(公告)号:US20120166729A1
公开(公告)日:2012-06-28
申请号:US12975640
申请日:2010-12-22
申请人: Greggory D. Donley
发明人: Greggory D. Donley
IPC分类号: G06F12/08
CPC分类号: G06F12/084
摘要: A method and apparatus for controlling affinity of subcaches is disclosed. When a core compute unit evicts a line of victim data, a prioritized search for space allocation on available subcaches is executed, in order of proximity between the subcache and the compute unit. The victim data may be injected into an adjacent subcache if space is available. Otherwise, a line may be evicted from the adjacent subcache to make room for the victim data or the victim data may be sent to the next closest subcache. To retrieve data, a core compute unit sends a Tag Lookup Request message directly to the nearest subcache as well as to a cache controller, which controls routing of messages to all of the subcaches. A Tag Lookup Response message is sent back to the cache controller to indicate if the requested data is located in the nearest sub-cache.
摘要翻译: 公开了一种用于控制子程序的亲和性的方法和装置。 当核心计算单元驱逐受害者数据行时,按照子程序和计算单元之间的邻近顺序执行对可用子对象上的空间分配的优先搜索。 如果空间可用,受害者数据可能会被注入到相邻的子程序中。 否则,可能会从相邻的子程序中删除一行,以便为受害者数据腾出空间,或者将受害者数据发送到下一个最接近的子程序。 为了检索数据,核心计算单元将代码查找请求消息直接发送到最近的子程序缓存以及缓存控制器,该缓存控制器控制消息到所有子程序的路由。 标签查找响应消息被发回到高速缓存控制器以指示所请求的数据是否位于最近的子缓存中。
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公开(公告)号:US5537418A
公开(公告)日:1996-07-16
申请号:US29864
申请日:1993-03-11
申请人: Greggory D. Donley
发明人: Greggory D. Donley
CPC分类号: H04J3/0685 , H04J3/062 , H04L12/422
摘要: An array of Digital data processing nodes are shown arrayed in at least one node-ring where each node has its own transmission-clock which is approximately the same frequency as the transmission-clock of other nodes in the ring and where data is transferred in data-packets, combined with this is a data-transmission-resynchronizing stage featuring "circular FIFO" arrangement.
摘要翻译: 数字数据处理节点的阵列被示出为排列在至少一个节点环中,其中每个节点具有其自己的传输时钟,其频率与环中其他节点的传输时钟大致相同,并且数据在数据中传输 与此相结合的是具有“循环FIFO”排列的数据传输 - 再同步阶段。
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公开(公告)号:US08732410B2
公开(公告)日:2014-05-20
申请号:US12962156
申请日:2010-12-07
申请人: Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
发明人: Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
IPC分类号: G06F12/08
CPC分类号: G06F12/084 , G06F12/0822 , G06F12/0833 , Y02D10/13
摘要: A method and apparatus for accelerated shared data migration between cores. Using an Always Migrate protocol, when a migratory probe hits a directory entry in either modified or owned state, the entry is transitioned to an owned state, and a source done command is sent without sending cache block ownership or state information to the directory.
摘要翻译: 一种用于加速内核之间共享数据迁移的方法和装置。 使用始终迁移协议,当迁移探测器以修改或归属状态命中目录条目时,该条目将转换为所有状态,并且发送源完成命令,而不向缓存目录发送缓存块所有权或状态信息。
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公开(公告)号:US07881303B2
公开(公告)日:2011-02-01
申请号:US11610191
申请日:2006-12-13
CPC分类号: H04L1/0011 , H04L1/0007 , H04L1/0061 , H04L1/18
摘要: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
摘要翻译: 在一个实施例中,节点包括分组调度器,其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据,其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组,其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定,取决于要发送的分组的可用性。 在另一个实施例中,接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。
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公开(公告)号:US20080148131A1
公开(公告)日:2008-06-19
申请号:US11610191
申请日:2006-12-13
CPC分类号: H04L1/0011 , H04L1/0007 , H04L1/0061 , H04L1/18
摘要: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
摘要翻译: 在一个实施例中,节点包括分组调度器,其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据,其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组,其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定,取决于要发送的分组的可用性。 在另一个实施例中,接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。
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公开(公告)号:US07293141B1
公开(公告)日:2007-11-06
申请号:US11048350
申请日:2005-02-01
申请人: Greggory D. Donley
发明人: Greggory D. Donley
CPC分类号: G06F12/0895 , G06F2212/271
摘要: Techniques for improving cache latency include distributing cache lines across regions of the cache having various latencies. The latencies of the regions may vary as a function of the distance between an individual region of the cache and a cache controller. The cache controller may predict an addressable unit of interest for a next access to a data line stored in a cache line. The predicted addressable unit of interest is stored in a region of the cache having the lowest latency as compared to other regions of the cache. The addressable unit of interest may be a most-recently used addressable unit, an addressable unit sequentially following a most-recently used addressable unit, or determined by other criterion. The invention contemplates using at least one control bit to indicate which addressable unit is stored in the region having the lowest latency.
摘要翻译: 用于改进高速缓存延迟的技术包括在具有不同延迟的缓存的区域上分配高速缓存行。 区域的延迟可以随高速缓存的单个区域和高速缓存控制器之间的距离的函数而变化。 高速缓存控制器可以预测用于对存储在高速缓存行中的数据线的下一次访问的可寻址单元。 与高速缓存的其他区域相比,预期的可寻址单元被存储在具有最低延迟的高速缓存的区域中。 感兴趣的可寻址单元可以是最近使用的可寻址单元,顺序地跟随最近使用的可寻址单元或由其他标准确定的可寻址单元。 本发明设想使用至少一个控制位来指示在具有最低延迟的区域中存储哪个可寻址单元。
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公开(公告)号:US5896052A
公开(公告)日:1999-04-20
申请号:US912302
申请日:1997-05-27
申请人: Manoj Gujral , Greggory D. Donley , Paul N. Israel
发明人: Manoj Gujral , Greggory D. Donley , Paul N. Israel
CPC分类号: H03K3/0375 , G06F1/04 , G11C7/22 , G11C8/06
摘要: A multi-clock pulse synchronizer circuit with and IN-section receiving and storing prescribed in-pulses and input clock signals and responsively outputting intermediate pulses; and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals, for better avoiding metastability.
摘要翻译: 一个多时钟脉冲同步器电路,具有IN部分,接收和存储规定的脉冲和输入时钟信号,并且响应地输出中间脉冲; 以及用于接收和存储中间脉冲的OUT部分,与某些输出时钟信号同步并对其进行处理以产生某些输出信号,以更好地避免亚稳态。
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公开(公告)号:US5761446A
公开(公告)日:1998-06-02
申请号:US518353
申请日:1995-06-14
申请人: Greggory D. Donley , Manoj Gujral
发明人: Greggory D. Donley , Manoj Gujral
IPC分类号: G06F13/362 , G06F13/14
CPC分类号: G06F13/3625
摘要: In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sup.B before reattempting such access, with each said time period T.sup.B being provided by the random number generator so as to likely differentiate from competing agents.
摘要翻译: 在多处理器计算机系统中,许多“代理”可以竞争访问“资源”,一种改善“活锁”并防止任何此类代理人不适应于此类访问的方法,该方法包括:将系统安排到 包括连接多个处理器的仲裁单元和连接多个处理器的公共系统总线,以及包括在每个处理器中的回避单元,并且包括随机数生成器和自动“随机回退”,其导致无法保护访问的代理等待一个或 在重新尝试此类访问之前更多地给出随机时间段TB,其中每个所述时间段TB由随机数发生器提供,以便可能与竞争代理区分开。
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公开(公告)号:US20120144122A1
公开(公告)日:2012-06-07
申请号:US12962156
申请日:2010-12-07
申请人: Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
发明人: Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
CPC分类号: G06F12/084 , G06F12/0822 , G06F12/0833 , Y02D10/13
摘要: A method and apparatus for accelerated shared data migration between cores is disclosed.
摘要翻译: 公开了一种用于在核之间加速共享数据迁移的方法和装置。
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