公开(公告)号：US20070113019A1

公开(公告)日：2007-05-17

申请号：US11282093

申请日：2005-11-17

申请人： Bruce Beukema ,  Michael Bar-Joshua ,  Alexander Mesh ,  Shaul Yifrach

发明人： Bruce Beukema ,  Michael Bar-Joshua ,  Alexander Mesh ,  Shaul Yifrach

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F9/3834 ,  G06F12/126

摘要： A circuit arrangement and method selectively reorder speculatively issued memory read requests being communicated to a lower memory level in a multi-level memory architecture. In particular, a memory read request that has been speculatively issued to a lower memory level prior to completion of a cache lookup operation initiated in a cache memory in a higher memory level may be reordered ahead of at least one previously received and pending request awaiting communication to the lower memory level. By doing so, the latency associated with the memory read request is reduced when the request results in a cache miss in the higher level memory, and as a result, system performance is improved.

摘要翻译： 电路布置和方法选择性地重新排序在多级存储器体系结构中被推送的存储器读请求被传送到较低存储器级。 特别地，在高级存储器级别的高速缓冲存储器中启动的高速缓存查找操作完成之前被推测地发布到较低存储器级别的存储器读取请求可以在至少一个先前接收到的等待通信的等待请求之前重新排序 到较低的内存级别。 通过这样做，当请求导致高级存储器中的高速缓存未命中时，与存储器读取请求相关联的延迟被减少，结果提高了系统性能。

公开(公告)号：US20100226420A1

公开(公告)日：2010-09-09

申请号：US12397790

申请日：2009-03-04

申请人： Etai Adar ,  Michael Bar-Joshua ,  David Stauffer

发明人： Etai Adar ,  Michael Bar-Joshua ,  David Stauffer

IPC分类号： H04L27/01 ,  H04B17/00

CPC分类号： H04L7/042 ,  H04L1/20 ,  H04L7/046

摘要： For example, a method of detecting frame marker quality includes: detecting, in a bit-stream sent from a first component to a second component of a common hardware unit, a frame marker having a bit pattern different from an uncorrupted frame marker specified by a communication protocol; and assigning a quality level indicator to the frame marker based on a difference between said bit pattern and a bit pattern of said uncorrupted frame marker.

摘要翻译： 例如，检测帧标记质量的方法包括：在从第一分量发送到公共硬件单元的第二分量的比特流中检测具有不同于由 通信协议; 以及基于所述位模式和所述未损坏帧标记的位模式之间的差异，将质量水平指示符分配给帧标记。

公开(公告)号：US07734854B2

公开(公告)日：2010-06-08

申请号：US11969475

申请日：2008-01-04

申请人： Etai Adar ,  Michael Bar-Joshua ,  Ilya Granovsky ,  Shaul Yifrach

发明人： Etai Adar ,  Michael Bar-Joshua ,  Ilya Granovsky ,  Shaul Yifrach

IPC分类号： G06F13/36

CPC分类号： G06F13/362

摘要： Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.

摘要翻译： 一些实施例包括例如处理事务的设备，系统和方法。 在一些说明性实施例中，处理计算系统中的事务的装置可以包括主单元，用于根据至少第一和第二仲裁方案通过请求总线发出读请求和写请求之间进行仲裁。 由主单元根据第一仲裁方案发出的读和写请求之间的第一比率可以不同于主单元根据第二仲裁方案发出的读和写请求之间的第二比率。