公开(公告)号：US08856498B2

公开(公告)日：2014-10-07

申请号：US13220006

申请日：2011-08-29

申请人： Atsushi Fusejima ,  Norihito Gomyo

发明人： Atsushi Fusejima ,  Norihito Gomyo

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/34

CPC分类号： G06F12/0862 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/34 ,  G06F9/383

摘要： A prefetch request circuit is provided in a processor device. The processor device has hierarchized storage areas and can prefetch data of address to be used between appropriate storage areas among the storage areas, when executing respective instruction flows obtained by multi-flow expansion for one instruction at a time of decoding of the instruction. The prefetch request circuit includes a latch unit to hold, when a state in which the respective instruction flows to access the storage area are executed with a maximum specifiable data transfer volume is specified, the state during a time period of the multi-flow expansion; and a prefetch request signal output unit to output a prefetch request signal to request the prefetch every time when the instruction flow is executed, based on an output signal of the latch unit and a signal indicating an execution timing of the respective instruction flows.

摘要翻译： 在处理器设备中提供预取请求电路。 处理器装置具有层次化的存储区域，并且当在指令解码时执行通过多流程扩展获得的用于一个指令的各个指令流时，可以预取在存储区域中的适当存储区域之间使用的地址数据。 预取请求电路包括：锁存单元，当指定以最大可指定数据传送量执行相应指令访问存储区域的状态时，保持多流程扩展期间的状态; 以及预取请求信号输出单元，用于基于所述锁存单元的输出信号和指示各个指令流的执行定时的信号，输出预取请求信号，以在每次执行指令流时请求预取。

公开(公告)号：US07523358B2

公开(公告)日：2009-04-21

申请号：US11153427

申请日：2005-06-16

申请人： Norihito Gomyo

发明人： Norihito Gomyo

IPC分类号： G06F11/00

CPC分类号： G06F11/0751 ,  G06F11/0721 ,  G06F11/0772 ,  G06F11/0781

摘要： In the instruction control apparatus having an instruction processing suspension unit and an error detection unit, in order to improve the reliability of the apparatus, the apparatus is configured in such a way that when an error occurs to certain hardware resources in the instruction processing apparatus, error detection is conducted if instruction processing is under way, but error detection is deterred if instruction processing is in suspension, and the scope of the error which cannot be deterred during the suspension of instruction processing is made narrower than the scope of the error which cannot be deterred during instruction processing.

摘要翻译： 在具有指令处理暂停单元和错误检测单元的指令控制装置中，为了提高装置的可靠性，该装置被配置为当指令处理装置中的某些硬件资源发生错误时， 如果指令处理正在进行，则进行错误检测，但是如果指令处理暂停，则会发生错误检测，并且在暂停指令处理时不能阻止的错误范围比不能进行的错误范围窄 在指令处理期间被阻止。

公开(公告)号：US06789185B1

公开(公告)日：2004-09-07

申请号：US09460457

申请日：1999-12-13

申请人： Norihito Gomyo ,  Aiichiro Inoue

发明人： Norihito Gomyo ,  Aiichiro Inoue

IPC分类号： G06F922

CPC分类号： G06F9/3017

摘要： A control reservation station stores the control information of a micro program to control one or more flows of an instruction process and controls each flow using the control information. A data buffer stores data to be used to control each flow and outputs the data at an appropriate timing.

摘要翻译： 控制预约站存储微程序的控制信息以控制指令处理的一个或多个流程，并使用控制信息来控制每个流程。 数据缓冲器存储要用于控制每个流的数据，并在适当的时刻输出数据。