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公开(公告)号：US08001362B2
公开(公告)日：2011-08-16
申请号：US12633108
申请日：2009-12-08
CPC分类号： G06F9/3851 , G06F9/3013 , G06F9/3857 , G06F11/3466 , G06F2201/88
摘要： A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.
摘要翻译： 处理单元包括多个线程执行单元，每个线程执行单元具有用于测量执行指令的各种类型的事件的性能分析电路和用于控制执行指令完成的提交堆栈输入单元，并且每个线程执行单元执行具有多个 指令，用于通过每个线程执行单元的执行来存储存储在每个提交栈输入单元中的完成候选的指令的提交范围寄存器，并且执行用于完成包括在该线程中的指令的处理;线程选择装置，用于发送指令的提交事件 涉及在对存储在提交范围寄存器中的指令执行提交处理时对应于指令的每个线程执行单元中提供的性能分析电路。
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2.发明授权公开(公告)号：US08516223B2
公开(公告)日：2013-08-20
申请号：US12801868
申请日：2010-06-29
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3001 , G06F9/3885 , G06F9/3891
摘要： A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station.
摘要翻译： 优先电路连接到保留站和处理不同的操作和调度的多个算术单元，当确定指示只能由特定算术单元执行指令的可执行标志被打开时，指令 算术单元，其与特定运算单元不同，并且根据由指令解码器和保留站执行的输入，其队列空闲。
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公开(公告)号：US20100088491A1
公开(公告)日：2010-04-08
申请号：US12633108
申请日：2009-12-08
CPC分类号： G06F9/3851 , G06F9/3013 , G06F9/3857 , G06F11/3466 , G06F2201/88
摘要： A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.
摘要翻译： 处理单元包括多个线程执行单元，每个线程执行单元具有用于测量执行指令的各种类型的事件的性能分析电路和用于控制执行指令完成的提交堆栈输入单元，并且每个线程执行单元执行具有多个 指令，用于通过每个线程执行单元的执行来存储存储在每个提交栈输入单元中的完成候选的指令的提交范围寄存器，并且执行用于完成包括在该线程中的指令的处理;线程选择装置，用于发送指令的提交事件 涉及在对存储在提交范围寄存器中的指令执行提交处理时对应于指令的每个线程执行单元中提供的性能分析电路。
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公开(公告)号：US08856498B2
公开(公告)日：2014-10-07
申请号：US13220006
申请日：2011-08-29
申请人： Atsushi Fusejima , Norihito Gomyo
发明人： Atsushi Fusejima , Norihito Gomyo
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/34 , G06F9/383
摘要： A prefetch request circuit is provided in a processor device. The processor device has hierarchized storage areas and can prefetch data of address to be used between appropriate storage areas among the storage areas, when executing respective instruction flows obtained by multi-flow expansion for one instruction at a time of decoding of the instruction. The prefetch request circuit includes a latch unit to hold, when a state in which the respective instruction flows to access the storage area are executed with a maximum specifiable data transfer volume is specified, the state during a time period of the multi-flow expansion; and a prefetch request signal output unit to output a prefetch request signal to request the prefetch every time when the instruction flow is executed, based on an output signal of the latch unit and a signal indicating an execution timing of the respective instruction flows.
摘要翻译： 在处理器设备中提供预取请求电路。 处理器装置具有层次化的存储区域，并且当在指令解码时执行通过多流程扩展获得的用于一个指令的各个指令流时，可以预取在存储区域中的适当存储区域之间使用的地址数据。 预取请求电路包括：锁存单元，当指定以最大可指定数据传送量执行相应指令访问存储区域的状态时，保持多流程扩展期间的状态; 以及预取请求信号输出单元，用于基于所述锁存单元的输出信号和指示各个指令流的执行定时的信号，输出预取请求信号，以在每次执行指令流时请求预取。
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公开(公告)号：US20110314262A1
公开(公告)日：2011-12-22
申请号：US13220006
申请日：2011-08-29
申请人： Atsushi FUSEJIMA , Norihito Gomyo
发明人： Atsushi FUSEJIMA , Norihito Gomyo
IPC分类号： G06F9/30
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/34 , G06F9/383
摘要： A prefetch request circuit is provided in a processor device. The processor device has hierarchized storage areas and can prefetch data of address to be used between appropriate storage areas among the storage areas, when executing respective instruction flows obtained by multi-flow expansion for one instruction at a time of decoding of the instruction. The prefetch request circuit includes a latch unit to hold, when a state in which the respective instruction flows to access the storage area are executed with a maximum specifiable data transfer volume is specified, the state during a time period of the multi-flow expansion; and a prefetch request signal output unit to output a prefetch request signal to request the prefetch every time when the instruction flow is executed, based on an output signal of the latch unit and a signal indicating an execution timing of the respective instruction flows.
摘要翻译： 在处理器设备中提供预取请求电路。 处理器装置具有层次化的存储区域，并且当在指令解码时执行通过多流程扩展获得的用于一个指令的各个指令流时，可以预取在存储区域中的适当存储区域之间使用的地址数据。 预取请求电路包括：锁存单元，当指定以最大可指定数据传送量执行相应指令访问存储区域的状态时，保持多流程扩展期间的状态; 以及预取请求信号输出单元，用于基于所述锁存单元的输出信号和指示各个指令流的执行定时的信号，输出预取请求信号，以在每次执行指令流时请求预取。
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公开(公告)号：US20100332802A1
公开(公告)日：2010-12-30
申请号：US12801868
申请日：2010-06-29
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3001 , G06F9/3885 , G06F9/3891
摘要： A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station.
摘要翻译： 优先电路连接到保留站和处理不同的操作和调度的多个算术单元，当确定指示只能由特定算术单元执行指令的可执行标志被打开时，指令 算术单元，其与特定运算单元不同，并且根据由指令解码器和保留站执行的输入，其队列空闲。
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