公开(公告)号：US07062641B1

公开(公告)日：2006-06-13

申请号：US09758540

申请日：2001-01-10

Applicant: Harish R. Devanagondi ,  Rajesh Patil ,  Sanjeev Mahalawat ,  Jianyong Sun

Inventor： Harish R. Devanagondi ,  Rajesh Patil ,  Sanjeev Mahalawat ,  Jianyong Sun

IPC: G06F7/499

CPC classification number: H03M13/09

Abstract: Unified exception handling may be provided by processing a data packet through at least two pipelined processing stages in a data packet processor such as a switch, router, bridge, or similar network device, each of the data packets having associated with it (while it is being processed) an exception map disposed in a memory of the network device. The bits in the exception map are set, modified, or reset in response to exception conditions detected at the various processing stages. After the packet has been fully processed, an exception handler takes as an input the exception map and further processes the packet in response to the state of the exception map.

Abstract translation: 可以通过在数据分组处理器（例如交换机，路由器，网桥或类似网络设备）中的至少两个流水线处理阶段处理数据分组来提供统一的异常处理，每个数据分组与其相关联 被处理）布置在网络设备的存储器中的异常映射。 响应于在各种处理阶段检测到的异常情况，异常映射中的位被设置，修改或重置。 在数据包被完全处理之后，异常处理程序将异常映射作为输入，并响应于异常映射的状态进一步处理数据包。

公开(公告)号：US07464254B2

公开(公告)日：2008-12-09

申请号：US10755188

申请日：2004-01-08

Applicant: Harshvardhan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Kennedy Arora

Inventor： Harshvardhan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Kennedy Arora

IPC: G06F7/00

CPC classification number: G06F17/30982 ,  G06F7/00 ,  G06F17/30985

Abstract: A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a decoder coupled to the general purpose register file to decode a set of instructions specified by the instruction sequencer, and a state machine unit coupled to the decoder and having state machine registers to store one or more state machines and state machine execution hardware coupled to the state machine registers to evaluate the one or more state machines in response to executing one or more of the set of instructions and based on information from one or both of the decoder and the general purpose register file.

Abstract translation: 公开了一种规则处理器及其使用方法。 在一个实施例中，规则处理器包括通用寄存器文件，提供指令的指令定序器，耦合到通用寄存器文件的解码器，以对由指令定序器指定的一组指令进行解码;以及状态机单元， 解码器，并且具有状态机寄存器，用于存储耦合到状态机寄存器的一个或多个状态机和状态机执行硬件，以响应于执行该组指令中的一个或多个并且基于来自一个指令的信息来评估一个或多个状态机 或解码器和通用寄存器文件两者。

公开(公告)号：US20050012521A1

公开(公告)日：2005-01-20

申请号：US10755048

申请日：2004-01-08

Applicant: Harshvardhan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Arora

Inventor： Harshvardhan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Arora

IPC: G05B19/042 ,  G05B19/045 ,  G06F7/38

CPC classification number: G06F7/00 ,  G06F17/30985

Abstract: Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.

Abstract translation: 本发明的实施例提供了一种可编程FSA构建块，其具有在其中实现的多个可编程寄存器和相关联的逻辑，其提供对多个数据流进行任意大小的复杂RE的上下文评估的能力。 本发明的实施例提供了完全可编程硬件，其中RE的所有状态都被实例化，并且所有状态都完全连接。 对于一个实施例，构建块具有固定数量的状态以便于在芯片上实现。 对于这样的实施例，在两个或更多个FSA构建块上实现具有过多状态的RE，然后将FSA构建块缝合在一起以实现RE的评估。 对于一个实施例，具有小于构建块的固定状态数量的状态数量的两个或更多个RE可以用单个构建块来实现。

公开(公告)号：US06489975B1

公开(公告)日：2002-12-03

申请号：US09338799

申请日：1999-06-23

Applicant: Rajesh Patil ,  Robert Shaver

Inventor： Rajesh Patil ,  Robert Shaver

IPC: G09G500

CPC classification number: G06F3/0481

Abstract: A system, method and computer readable medium for navigating between multiple open windows in a graphical user interface (GUI) of a user program. The system presents a selectable graphical display within a program GUI corresponding to opened windows within that program. The user may select which of one or more opened windows to display by selecting the selectable graphical display corresponding to that window. The selectable graphical display may comprise a tab having text or other graphical data indicating the window to which it corresponds. The selectable graphical display corresponding to the window that is active within the program GUI may appear different from the other selectable graphical displays and may also comprise a kill box that enables the user to close that window. Additionally, a selection tool may be provided. When the selection tool is placed by the user over each selectable graphical display, a kill box may also be presented with that selectable graphical display to enable the user to close the window corresponding to that selectable graphical display.

Abstract translation: 一种用于在用户程序的图形用户界面（GUI）中的多个打开的窗口之间导航的系统，方法和计算机可读介质。 该系统在对应于该程序中打开的窗口的程序GUI中呈现可选择的图形显示。 用户可以通过选择对应于该窗口的可选图形显示来选择要显示的一个或多个打开的窗口中的哪一个。 可选择的图形显示可以包括具有指示与其对应的窗口的文本或其他图形数据的标签。 对应于程序GUI内活动的窗口的可选图形显示可能与其他可选图形显示不同，并且还可以包括使得用户能够关闭该窗口的杀箱。 另外，可以提供选择工具。 当选择工具由用户放置在每个可选择的图形显示器上时，杀手盒也可以呈现该可选择的图形显示器，以使用户能够关闭对应于该可选图形显示器的窗口。