公开(公告)号：US08154433B2

公开(公告)日：2012-04-10

申请号：US12899660

申请日：2010-10-07

Applicant: Roderick McLachlan ,  Teng-Hee Lee

Inventor： Roderick McLachlan ,  Teng-Hee Lee

IPC: H03M1/10

CPC classification number: H03M1/0612 ,  H03M1/76 ,  H03M1/808

Abstract: A force/sense voltage-mode DAC coupled with multiple transconductance amplifiers that generate a correction current injected to a node in one of the DAC cells is discussed. The correction current injected into the DAC cell may reduce nonlinearity produced by biasing current to the operational amplifiers in the DAC.

Abstract translation: 讨论了耦合到多个跨导放大器的力/感测电压模式DAC，其产生注入到DAC单元之一中的节点的校正电流。 注入到DAC单元中的校正电流可以减小通过偏置电流到DAC中的运算放大器产生的非线性。

公开(公告)号：US20120050084A1

公开(公告)日：2012-03-01

申请号：US13005274

申请日：2011-01-12

Applicant: Roderick McLachlan

Inventor： Roderick McLachlan

IPC: H03M1/78

CPC classification number: H03M1/0845 ,  H03M1/76 ,  H03M1/785 ,  H03M1/808

Abstract: A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. A first force switch may be coupled to an output of a first operational amplifier and an associated sense switch may be coupled to an inverting input of the first operational amplifier. A second force switch may be coupled to an output of a second operational amplifier and an associated sense switch may be coupled to an inverting input of the second operational amplifier. The force switches may provide selectively conductive paths to permit either operational amplifier to drive a given cell.

Abstract translation: 数模转换器（DAC）包括一对运算放大器，每个运算放大器具有耦合到参考电压的第一输入。 DAC包括多个开关控制单元，每个单元包括电阻器和两个力/感测开关对。 第一力开关可以耦合到第一运算放大器的输出，并且相关联的感测开关可以耦合到第一运算放大器的反相输入。 第二力开关可以耦合到第二运算放大器的输出，并且相关联的感测开关可以耦合到第二运算放大器的反相输入。 力开关可以提供选择性的导电路径，以允许运算放大器驱动给定的单元。

公开(公告)号：US20120050080A1

公开(公告)日：2012-03-01

申请号：US12899660

申请日：2010-10-07

Applicant: Roderick MCLACHLAN ,  Teng-Hee LEE

Inventor： Roderick MCLACHLAN ,  Teng-Hee LEE

IPC: H03M1/06 ,  H03M1/78 ,  H03M1/66

CPC classification number: H03M1/0612 ,  H03M1/76 ,  H03M1/808

Abstract: A force/sense voltage-mode DAC coupled with multiple transconductance amplifiers that generate a correction current injected to a node in one of the DAC cells is discussed. The correction current injected into the DAC cell may reduce nonlinearity produced by biasing current to the operational amplifiers in the DAC.

Abstract translation: 讨论了耦合到多个跨导放大器的力/感测电压模式DAC，其产生注入到DAC单元之一中的节点的校正电流。 注入到DAC单元中的校正电流可以减小通过偏置电流到DAC中的运算放大器产生的非线性。

公开(公告)号：US20120013492A1

公开(公告)日：2012-01-19

申请号：US13168017

申请日：2011-06-24

Applicant: Roderick MCLACHLAN ,  Michael COLN

Inventor： Roderick MCLACHLAN ,  Michael COLN

IPC: H03M1/06

CPC classification number: H03M1/0621 ,  H03M1/1047 ,  H03M1/804 ,  H03M1/808

Abstract: The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal.

Abstract translation: 本发明提供耦合到转换器的系统误差校正网络。 转换器可能会显示系统的非线性误差，并且系统误差校正网络对于非线性误差，形成像反失真函数一样的校正变换函数。 然后，系统误差校正网络根据参考变量对校正变换函数进行缩放，其中非线性误差的大小与参考变量相关。 然后将缩放的校正变换函数应用于转换器路径，以便产生校正的模拟输出信号。

公开(公告)号：US07884747B2

公开(公告)日：2011-02-08

申请号：US12483295

申请日：2009-06-12

Applicant: Roderick McLachlan

Inventor： Roderick McLachlan

IPC: H03M1/78

CPC classification number: H03M1/0845 ,  H03M1/76 ,  H03M1/785 ,  H03M1/808

Abstract: A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a respective high or low reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. Within each cell, all four switches are coupled to the resistor. A first force switch is coupled to an output of a first op amp and an associated sense switch is coupled to an inverting input of the first op amp. A second force switch is coupled to an output of a second op amp and an associated sense switch is coupled to an inverting input of the second op amp. Thus, the force switches provide selectively conductive paths to permit either op amp to drive a given cell. When an op amp drives particular cells, sense switches generate multiple a feedback paths to the driving op amp, which permits the op amp to drive the selected cell resistors at voltages that overcomes any voltage losses induces by associated force switches, and cancels the effect of any variation in the voltage losses induced by different force switches. The switch-controlled cells find application in a variety of DAC architectures, including binary weighted R2R architectures, equally-weighted segmented architectures or hybrid architectures that blend principles of R2R and segmented architectures.

Abstract translation: 数模转换器（DAC）包括一对运算放大器，每个运算放大器具有耦合到相应的高或低参考电压的第一输入。 DAC包括多个开关控制单元，每个单元包括电阻器和两个力/感测开关对。 在每个单元内，所有四个开关都耦合到电阻器。 第一力开关耦合到第一运算放大器的输出，相关联的感测开关耦合到第一运算放大器的反相输入端。 第二力开关耦合到第二运算放大器的输出，相关联的感测开关耦合到第二运算放大器的反相输入端。 因此，力开关提供选择性的导电路径以允许运算放大器驱动给定的电池。 当运算放大器驱动特定单元时，感测开关产生到驱动运算放大器的多个反馈路径，这允许运算放大器以克服由相关力开关引起的任何电压损耗的电压驱动所选择的单元电阻，并且消除任何 由不同的力开关引起的电压损耗的变化。 交换机控制的小区在各种DAC体系结构中找到应用，包括二进制加权的R2R架构，同等加权的分段架构或混合R2R和分段架构的混合体系结构。