UNIFIED DRIVING METHOD AND UNIFIED DRIVER APPARATUS
    11.
    发明申请
    UNIFIED DRIVING METHOD AND UNIFIED DRIVER APPARATUS 有权
    统一驾驶方法和统一驾驶装置

    公开(公告)号:US20140165079A1

    公开(公告)日:2014-06-12

    申请号:US14180894

    申请日:2014-02-14

    CPC classification number: G06F9/54 G06F9/44521

    Abstract: The present invention provides a technical solution for a unified driver used in a handheld device. An embodiment of the technical solution may comprise a unified driving method used in a handheld device, which method may comprise: determining driver types of currently installed hardware; setting a current dispatch table on the basis of the driver type and a unified dispatch table suitable for multiple hardware and driving corresponding hardware or software by calling the current dispatch table.

    Abstract translation: 本发明提供了用于手持设备中的统一驱动程序的技术方案。 技术方案的实施例可以包括在手持设备中使用的统一驱动方法,该方法可以包括:确定当前安装的硬件的驱动器类型; 基于驱动程序类型设置当前调度表,并通过调用当前调度表来适用于多个硬件并驱动相应的硬件或软件的统一调度表。

    CIRCUIT AND METHOD FOR GENERATING A BANDGAP REFERENCE VOLTAGE
    12.
    发明申请
    CIRCUIT AND METHOD FOR GENERATING A BANDGAP REFERENCE VOLTAGE 有权
    产生带宽参考电压的电路和方法

    公开(公告)号:US20140070788A1

    公开(公告)日:2014-03-13

    申请号:US14020949

    申请日:2013-09-09

    CPC classification number: G05F3/08 G05F3/22 G05F3/30

    Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.

    Abstract translation: 带隙参考电压发生器包括具有第一电阻器,第一分支和与第一分支平行的第二分支的双极组件。 第一分支包括具有耦合到固定电压的基极的第一双极晶体管。 第二分支包括具有耦合到固定电压的基极的第二双极晶体管和与第二双极晶体管串联耦合的第二电阻器。 差分模块耦合到第一和第二双极晶体管并且被配置为平衡第一和第二分支中的电流。 带隙参考电压在与第一电阻器连接的节点处输出。

    Circuit and method for generating a bandgap reference voltage
    13.
    发明授权
    Circuit and method for generating a bandgap reference voltage 有权
    用于产生带隙参考电压的电路和方法

    公开(公告)号:US09568933B2

    公开(公告)日:2017-02-14

    申请号:US14020949

    申请日:2013-09-09

    CPC classification number: G05F3/08 G05F3/22 G05F3/30

    Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.

    Abstract translation: 带隙参考电压发生器包括具有第一电阻器,第一分支和与第一分支平行的第二分支的双极组件。 第一分支包括具有耦合到固定电压的基极的第一双极晶体管。 第二分支包括具有耦合到固定电压的基极的第二双极晶体管和与第二双极晶体管串联耦合的第二电阻器。 差分模块耦合到第一和第二双极晶体管并且被配置为平衡第一和第二分支中的电流。 带隙参考电压在与第一电阻器连接的节点处输出。

    HS-CAN BUS CLOCK RECOVERY USING A TRACKING OSCILLATOR CIRCUIT
    15.
    发明申请
    HS-CAN BUS CLOCK RECOVERY USING A TRACKING OSCILLATOR CIRCUIT 有权
    HS-CAN总线时钟恢复使用跟踪振荡器电路

    公开(公告)号:US20130173949A1

    公开(公告)日:2013-07-04

    申请号:US13716029

    申请日:2012-12-14

    CPC classification number: G06F1/04 G06F3/044 G06F11/3051

    Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.

    Abstract translation: 一种用于恢复CAN总线的时钟频率的方法,所述方法包括:接收数据信号,其中所述数据信号包括至少一个状态转换; 检测状态转换; 以及调整由振荡器电路产生的时钟信号的频率,其中当检测到状态转换时调整频率,并且调整频率用于恢复CAN总线的时钟频率。

    CASCODE DRIVE CIRCUITRY
    16.
    发明申请
    CASCODE DRIVE CIRCUITRY 有权
    CASCODE驱动电路

    公开(公告)号:US20130169344A1

    公开(公告)日:2013-07-04

    申请号:US13657930

    申请日:2012-10-23

    CPC classification number: H03K17/102

    Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed

    Abstract translation: 驱动电路包括具有设计最大电压V2的开关晶体管和具有设计最大电压V1的共源共栅晶体管,其中共源共栅晶体管是与开关晶体管串联耦合的源极 - 漏极。 电路还包括耦合在中间电压节点和共源共栅晶体管的栅极之间的电流源。 如果驱动电路是低端驱动器,则中间电压节点接收设置在高电源电压Vhigh以下的中间电压Vmed,并满足以下条件:a)Vmed <= V2和b)Vhigh-Vmed <= V1。 如果驱动电路是高侧驱动器,则中间电压节点接收低于高电源电压的中间电压Vmed,并且符合以下条件:a)Vmed <= V1和b)Vhigh-Vmed <= V2。 该电路可以通过将高侧驱动器和低侧驱动器串联耦合而构造为推挽驱动器。

    HS-CAN bus clock recovery using a tracking oscillator circuit
    17.
    发明授权
    HS-CAN bus clock recovery using a tracking oscillator circuit 有权
    使用跟踪振荡器电路的HS-CAN总线时钟恢复

    公开(公告)号:US09032239B2

    公开(公告)日:2015-05-12

    申请号:US13716029

    申请日:2012-12-14

    CPC classification number: G06F1/04 G06F3/044 G06F11/3051

    Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.

    Abstract translation: 一种用于恢复CAN总线的时钟频率的方法,所述方法包括:接收数据信号,其中所述数据信号包括至少一个状态转换; 检测状态转换; 以及调整由振荡器电路产生的时钟信号的频率,其中当检测到状态转换时调整频率,并且调整频率用于恢复CAN总线的时钟频率。

    FULLY INTEGRATED CIRCUIT FOR GENERATING A RAMP SIGNAL
    18.
    发明申请
    FULLY INTEGRATED CIRCUIT FOR GENERATING A RAMP SIGNAL 有权
    用于产生RAMP信号的完全集成电路

    公开(公告)号:US20130169324A1

    公开(公告)日:2013-07-04

    申请号:US13648557

    申请日:2012-10-10

    CPC classification number: H03K4/502

    Abstract: A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal.

    Abstract translation: 完全集成的斜坡发生器电路包括第一电流发生器,其通过由周期信号的补码门控制的第一晶体管向第一电容器供电。 存储在第一电容器上的斜坡电压作为斜坡输出信号被缓冲到输出节点。 第二晶体管将输出节点耦合到第一电流发生器,并由周期信号进行栅极控制。 周期性信号在接收输入时钟信号和复位信号的触发器的输出端产生。 复位信号由比较器电路产生,比较器电路可操作以将第二电容器上的电压与参考电压进行比较。 第二电容器由第二电流源充电,并由被周期信号门控制的第三晶体管放电。

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