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公开(公告)号：US20240353882A1
公开(公告)日：2024-10-24
申请号：US18763940
申请日：2024-07-03
Applicant: Intel Corporation
Inventor： You LI , David DUARTE , Yongping FAN
IPC: G05F3/30
CPC classification number: G05F3/30
Abstract: A low power hybrid reverse (LPHR) bandgap reference (BGR) and digital temperature sensor (DTS) or a digital thermometer, which utilizes subthreshold metal oxide semiconductor (MOS) transistors.
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公开(公告)号：US12085972B1
公开(公告)日：2024-09-10
申请号：US17657462
申请日：2022-03-31
Applicant: Mixed-Signal Devices Inc.
Inventor： Rakesh Kumar Palani , Srikar Bhagavatula
IPC: G05F3/30
CPC classification number: G05F3/30
Abstract: Systems and methods for sampled band-gap reference voltage generators are described. An embodiment includes a band-gap reference voltage generator circuit that includes: a first load transistor, a second load transistor where the gates of the first and second load transistors are connected, a first bipolar transistor, a second bipolar transistor, where the bases of the first and second bipolar transistors are connected, a first capacitor where a first terminal of the first capacitor is connected to the emitter of the first bipolar transistor through a first switch and a second terminal of the first capacitor is connected to the emitter of the second bipolar transistor through a second switch.
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公开(公告)号：US11914411B2
公开(公告)日：2024-02-27
申请号：US17314637
申请日：2021-05-07
Applicant: Texas Instruments Incorporated
Inventor： Sandeep Shylaja Krishnan , Tallam Vishwanath , Akshay Yashwant Jadhav
CPC classification number: G05F3/265 , G05F3/222 , G05F3/225 , G05F3/30 , H03F3/45179
Abstract: A bandgap reference circuit includes first through fourth bipolar junction transistors (BJTs). The base and collector of the first BJT are shorted together. The second BJT is coupled to the first BJT via a first resistor. The base of the third BJT is coupled to the base of the first BJT. The base and collector of the fourth BJT are coupled together and also are coupled to the base of the second BJT. A second resistor is coupled to the fourth emitter of the fourth BJT. A third resistor is coupled to the second resistor and to the emitter of the second BJT. An operational amplifier has a first input coupled to the first resistor and the collector of the second BJT, a second input coupled to the emitter of the third BJT and the collector of the fourth BJT, and an output coupled to the collectors of the first and third BJTs.
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公开(公告)号：US11838012B2
公开(公告)日：2023-12-05
申请号：US17921432
申请日：2021-04-19
Applicant: ams International AG
Inventor： Vincenzo Leonardo
CPC classification number: H03K17/145 , G05F1/56 , G05F3/30 , H03K17/22
Abstract: A power on reset circuit comprises terminals for reference and supply potentials and a voltage divider coupled therebetween. First and second transistors of a bandgap circuit are resistively coupled to the reference potential terminal and have bases connected to the voltage divider. Current mirrors couple the collectors of the first and second transistors to an output terminal providing an output signal indicating a power on reset condition. A first compensation transistor is coupled between the collector of one of the transistors and the reference potential terminal, and a second compensation transistor is coupled between the output terminal and the reference potential terminal to compensate the effect of parasitic substrate currents in response to an external interference.
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公开(公告)号：US20230384813A1
公开(公告)日：2023-11-30
申请号：US18315506
申请日：2023-05-11
Applicant: Realtek Semiconductor Corporation
Inventor： Sheng-Wei LIN , Wei-Cheng TANG
Abstract: A low-dropout regulator circuit includes a reference circuit, an amplifying circuit, a power switch circuit, a feedback circuit, and a control circuit. The reference circuit is configured to generate a reference voltage. The amplifying circuit is configured to generate an amplifying voltage according to the reference voltage and a feedback voltage. The power switch circuit is configured to receive the amplifying voltage and generate an output voltage at an output terminal according to an input voltage. The feedback circuit is configured to generate the feedback voltage according to the output voltage. The control circuit is configured to control the power switch circuit according to the input voltage and a signal from the reference circuit.
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Patent Agency Ranking
公开(公告)号：US11768513B2
公开(公告)日：2023-09-26
申请号：US17818374
申请日：2022-08-09
Inventor： Chia Liang Tai
Abstract: A signal generating device including a first circuit coupled between a first reference voltage and a second reference voltage and arranged to generate a first current to a first BJT; a first control circuit connected to the first BJT and arranged to adjust the first current. The first circuit outputs a part of a temperature-dependent signal on an output terminal, and includes: a first active device having a first and a second connecting terminal coupled to the first BJT; a second active device having a first connecting terminal coupled to the first BJT, and a second connecting terminal coupled to a second reference voltage; a first amplifier having an input terminal coupled to the first BJT, and an output terminal coupled to the control terminal of the first active device; and a second control circuit coupled to the first circuit for controlling the temperature-dependent signal according to the first current.
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公开(公告)号：US11656643B2
公开(公告)日：2023-05-23
申请号：US17302785
申请日：2021-05-12
Applicant: NXP USA, Inc.
Inventor： Siamak Delshadpour , Xueyang Geng
Abstract: A circuit for converting a first voltage to a second voltage in a communication system is disclosed. The circuit includes a pass transistor including a first terminal, a second terminal and a gate, wherein the first terminal is coupled with the first voltage. The circuit is also includes an error amplifier. The error amplifier includes a first input that is coupled with a constant reference voltage and a second input that is coupled with a first switch that is coupled with an output port. A second switch is included and is coupled between the first voltage and an output of the error amplifier. The output of the error amplifier is coupled with the gate of the pass transistor. A third switch is included and is coupled between ground and the output of the error amplifier. The second switch is configured to be driven by a first one shot pulse generated from an input signal of the communication system and the third switch is configured to be driven by a second one shot pulse generated from the input signal.
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公开(公告)号：US10374647B1
公开(公告)日：2019-08-06
申请号：US15895648
申请日：2018-02-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jikai Chen , Yuan Rao , Yanli Fan
Abstract: A circuit includes a sensor configured to receive an input signal and to provide a sensor output signal in response to the received input signal. A plurality of mirror circuits are configured to receive the sensor output signal from the sensor and to generate mirror circuit output signals. The plurality of mirror circuits includes a first mirror circuit and at least a second mirror circuit. The first mirror circuit increases its respective mirror circuit output signal until its saturation value is reached. The second mirror circuit increases its respective mirror output signal if the sensor output signal is above a threshold value and until its saturation value is reached.
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公开(公告)号：US20190041471A1
公开(公告)日：2019-02-07
申请号：US15671080
申请日：2017-08-07
Applicant: LINEAR TECHNOLOGY HOLDINGS LLC
Inventor： Kalin V. LAZAROV , Robert C. Chiacchia
CPC classification number: G01R33/0029 , G01R19/2503 , G01R33/0082 , G01R35/007 , G05F1/468 , G05F3/02 , G05F3/30 , H01L23/562
Abstract: In a system and method for correcting a stress-impaired signal in a circuit, a calibration circuit produces a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a voltage proportional to absolute temperature. A set of reference values are generated based on these voltages. A gain correction factor is calculated based on a function of the set of reference values and a set of temperature-dependent values, and the stress-impaired signal is corrected based on the gain correction factor.
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公开(公告)号：US20180253118A1
公开(公告)日：2018-09-06
申请号：US15966176
申请日：2018-04-30
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shinya SANO , Masashi HORIGUCHI , Takahiro MIKI , Mitsuru HIRAKI
Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
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