公开(公告)号：US11641217B2

公开(公告)日：2023-05-02

申请号：US17421589

申请日：2019-01-22

Applicant: STMICROELECTRONICS SA ,  INSTITUT POLYTECHNIQUE DE BORDEAUX ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  UNIVERSITE DE BORDEAUX

Inventor： Jeremie Forest ,  Vincent Knopik ,  Eric Kerherve

IPC: H04B1/18 ,  H04B1/04 ,  H03F3/24

Abstract: In an embodiment method, a hybrid coupler comprises a first input receiving an analog signal, a second input receiving an additional analog signal phase shifted by 90° from the analog signal, and first and second outputs. The method comprises injecting into the second output a test signal having an initial test phase, iteratively generating a current test phase for the test signal, from the initial test phase to a final test phase equal to the initial test phase increased by at least one portion of one complete revolution, and, in each iteration, measuring the current peak value of the first output, and storing the current test phase and the current peak value as a maximum/minimum peak value if there is not a stored maximum/minimum peak value higher/lower than the current peak value, respectively, and determining a phase of the analog signal from the stored test phase.

公开(公告)号：US20230079355A1

公开(公告)日：2023-03-16

申请号：US17987280

申请日：2022-11-15

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc. ,  STMicroelectronics (Research & Development) Limited

Inventor： Darin K. Winterton ,  Donald Baxter ,  Andrew Hodgson ,  Gordon Lunn ,  Olivier Pothier ,  Kalyan-Kumar Vadlamudi-Reddy

IPC: H04N5/232

Abstract: A method includes dividing a field of view into a plurality of zones and sampling the field of view to generate a photon count for each zone of the plurality of zones, identifying a focal sector of the field of view and analyzing each zone to select a final focal object from a first prospective focal object and a second prospective focal object.

公开(公告)号：US11581303B2

公开(公告)日：2023-02-14

申请号：US16869840

申请日：2020-05-08

Applicant: STMicroelectronics SA

Inventor： Louise De Conti ,  Philippe Galy

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.

公开(公告)号：US11563424B2

公开(公告)日：2023-01-24

申请号：US17496548

申请日：2021-10-07

Applicant: STMICROELECTRONICS SA

Inventor： Jeremie Forest ,  Vincent Knopik

IPC: H03H11/16 ,  H03F3/24 ,  H04B1/3827 ,  H04W84/04

Abstract: In an embodiment, a method for determining the phase shift between a first signal and a second signal includes: delivering the first signal to a first input of a 90° hybrid coupler; delivering the second signal to a second input of the 90° hybrid coupler; determining a first piece of information relating to a power of a first output signal delivered to a first output of the 90° hybrid coupler; determining a second piece of information relating to a power of a second output signal delivered to a second output of the coupler; and adjusting the phase of the second signal until obtaining a calibrated phase for which the first piece of information is substantially equal to the second piece of information, wherein the first and second signals have identical frequencies, and wherein the phase shift between the first signal and the second signal is equal to the calibrated phase.

公开(公告)号：US20220360236A1

公开(公告)日：2022-11-10

申请号：US17662542

申请日：2022-05-09

Applicant: STMICROELECTRONICS SA

Inventor： Samia Ouyahia ,  Renaud Lemoine ,  Eric Wilhelm

IPC: H03F3/213 ,  H01L27/06 ,  H03F3/45 ,  H03F1/02

Abstract: According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.

公开(公告)号：US11444077B2

公开(公告)日：2022-09-13

申请号：US16696045

申请日：2019-11-26

Applicant: STMicroelectronics SA

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat ,  Agustin Monroy Aguirre

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/12 ,  H01L27/102 ,  H01L29/74 ,  H01L29/87

Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.

公开(公告)号：US20220179822A1

公开(公告)日：2022-06-09

申请号：US17457553

申请日：2021-12-03

Applicant: STMICROELECTRONICS SA ,  STMicroelectronics (Alps) SAS

Inventor： Michael Soulie ,  Thomas Martin

IPC: G06F15/78 ,  G06F1/08 ,  G06F1/14

Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.

公开(公告)号：US11355851B2

公开(公告)日：2022-06-07

申请号：US16889240

申请日：2020-06-01

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Frederic Gianesello ,  Didier Campos

IPC: H01Q9/04 ,  H01Q5/357 ,  H01Q1/22 ,  H01Q21/28

Abstract: A first independent unit includes a support substrate with an integrated network of electrical connections. An electronic integrated circuit chip is mounted above a front face of the support substrate. A second independent unit includes a dielectric support. The second independent unit is stacked above the first independent unit on a side of the front face of the first independent unit. An electromagnetic antenna includes an exciter element and a resonator element. The exciter element provided at the support substrate. The resonator element is provided at the dielectric support.

公开(公告)号：US20220158675A1

公开(公告)日：2022-05-19

申请号：US17421589

申请日：2019-01-22

Applicant: STMICROELECTRONICS SA ,  INSTITUT POLYTECHNIQUE DE BORDEAUX ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  UNIVERSITE DE BORDEAUX

Inventor： Jeremie Forest ,  Vincent Knopik ,  Eric Kerherve

IPC: H04B1/18 ,  H04B1/04 ,  H03F3/24

Abstract: In an embodiment method, a hybrid coupler comprises a first input receiving an analog signal, a second input receiving an additional analog signal phase shifted by 90° from the analog signal, and first and second outputs. The method comprises injecting into the second output a test signal having an initial test phase, iteratively generating a current test phase for the test signal, from the initial test phase to a final test phase equal to the initial test phase increased by at least one portion of one complete revolution, and, in each iteration, measuring the current peak value of the first output, and storing the current test phase and the current peak value as a maximum/minimum peak value if there is not a stored maximum/minimum peak value higher/lower than the current peak value, respectively, and determining a phase of the analog signal from the stored test phase.

公开(公告)号：US20220123781A1

公开(公告)日：2022-04-21

申请号：US17506320

申请日：2021-10-20

Applicant: STMICROELECTRONICS SA

Inventor： Jeremie Forest ,  Vincent Knopik

IPC: H04B1/58 ,  H04B1/401 ,  H01Q1/24

Abstract: In an embodiment, a circuit includes first, second, and third 90° hybrid couplers coupled between first and second antenna terminals, a pair of low-noise amplifiers (LNAs), and a pair of power amplifiers (PAs). The pair of LNAs is configured to receive first signals from the first and second antenna terminals and has an output configured to be coupled to a receive path. The second coupler is configured in power combiner mode for receiving the first signals. The pair of PAs is configured to transmit second signals via the first and second antenna terminals and has an input configured to be coupled to a transmit path. The third coupler is configured in power divider mode for transmitting the second signals.