公开(公告)号：US07689977B1

公开(公告)日：2010-03-30

申请号：US12423894

申请日：2009-04-15

Applicant: Guansong Zhang ,  Shimin Cui ,  Ettore Tiotto

Inventor： Guansong Zhang ,  Shimin Cui ,  Ettore Tiotto

IPC: G06F9/45

CPC classification number: G06F8/314 ,  G06F8/45

Abstract: The present disclosure is directed to a method for providing an OpenMP reduction implementation. The method may comprise creating an aggregate of at least one reduction variable in a parallel region or a work-sharing construct; defining a pointer variable, the pointer variable pointing to a dynamic array of the aggregate; creating an initialization routine, an outlined routine and a reduction accumulation routine; replacing the parallel region or the work-sharing construct with a runtime routine, the runtime routine taking a plurality of arguments including an address of the initialization routine, an address of the outlined routine, an address of the reduction accumulation routine, an address of the pointer variable, and a size of the aggregate; and executing the runtime routine when the at least one reduction variable is in the parallel region or the work-sharing construct.

Abstract translation: 本公开涉及一种用于提供OpenMP缩减实现的方法。 该方法可以包括在并行区域或工作共享构造中创建至少一个减少变量的聚合; 定义指针变量，指针变量指向聚合的动态数组; 创建初始化例程，概述例程和减少累积程序; 用运行时程序替换并行区域或工作共享结构，运行时程序采取多个参数，包括初始化例程的地址，概述的例程的地址，减少累积程序的地址， 指针变量和聚合体的大小; 以及当所述至少一个缩减变量在并行区域或所述工作共享构造中时执行所述运行时程序。

公开(公告)号：US20080229297A1

公开(公告)日：2008-09-18

申请号：US12129449

申请日：2008-05-29

Applicant: ROCH GEORGES ARCHAMBAULT ,  Shimin Cui

Inventor： ROCH GEORGES ARCHAMBAULT ,  Shimin Cui

IPC: G06F9/45

CPC classification number: G06F8/445 ,  G06F8/443 ,  G06F8/453

Abstract: A computer implemented method, system and computer program product for accessing threadprivate memory for threadprivate variables in a parallel program during program compilation. A computer implemented method for accessing threadprivate variables in a parallel program during program compilation includes aggregating threadprivate variables in the program, replacing references of the threadprivate variables by indirect references, moving address load operations of the threadprivate variables, and replacing the address load operations of the threadprivate variables by calls to runtime routines to access the threadprivate memory. The invention enables a compiler to minimize the runtime routines call times to access the threadprivate variables, thus improving program performance.

Abstract translation: 一种计算机实现的方法，系统和计算机程序产品，用于在程序编译期间在并行程序中访问线程私有变量的线程私有存储器。 在程序编译过程中，一种用于在并行程序中访问线程私有变量的计算机实现方法包括在程序中聚合线程私有变量，通过间接引用替代线程私有变量的引用，移动线程私有变量的地址加载操作，以及替换 threadprivate变量通过调用运行时程序访问线程私有内存。 本发明使得编译器能够最小化运行时程序调用时间以访问线程私有变量，从而提高程序性能。

公开(公告)号：US20070240137A1

公开(公告)日：2007-10-11

申请号：US11402556

申请日：2006-04-11

Applicant: Roch Archambault ,  Shimin Cui ,  Yaoqing Gao ,  Raul Silvera

Inventor： Roch Archambault ,  Shimin Cui ,  Yaoqing Gao ,  Raul Silvera

IPC: G06F9/45

CPC classification number: G06F8/4442

Abstract: A method of compiling source code. The method includes converting pointer-based access in the source code to array-based access in the source code in a first pass compilation of the source code. Information is collected for objects in the source code during the first pass compilation. Candidate objects in the source code are selected based on the collected information to form selected candidate objects. Global stride variables are created for the selected candidate objects. Memory allocation operations are updated for the selected candidate objects in a second pass compilation of the source code. Multiple-level pointer indirect references are replaced in the source code with multi-dimensional array indexed references for the selected candidate objects in the second pass compilation of the source code.

Abstract translation: 一种编译源代码的方法。 该方法包括在源代码的第一遍编译中将源代码中的基于指针的访问转换为源代码中的基于数组的访问。 在第一次编译期间，为源代码中的对象收集信息。 基于收集的信息来选择源代码中的候选对象以形成所选择的候选对象。 为所选候选对象创建全局步幅变量。 在源代码的第二遍编译中，针对所选候选对象更新内存分配操作。 在源代码的第二遍编译中，多级指针间接引用被替换为所选候选对象的多维数组索引引用的源代码。

公开(公告)号：US20060048103A1

公开(公告)日：2006-03-02

申请号：US10930037

申请日：2004-08-30

Applicant: Roch Archambault ,  Shimin Cui ,  Yaoqing Gao ,  Raul Silvera

Inventor： Roch Archambault ,  Shimin Cui ,  Yaoqing Gao ,  Raul Silvera

IPC: G06F9/44

CPC classification number: G06F8/4442

Abstract: Inter-procedural strength reduction is provided by a mechanism of the present invention to improve data cache performance. During a forward pass, the present invention collects information of global variables and analyzes the usage pattern of global objects to select candidate computations for optimization. During a backward pass, the present invention remaps global objects into smaller size new global objects and generates more cache efficient code by replacing candidate computations with indirect or indexed reference of smaller global objects and inserting store operations to the new global objects for each computation that references the candidate global objects.

公开(公告)号：US10101979B2

公开(公告)日：2018-10-16

申请号：US13545649

申请日：2012-07-10

Applicant: Shimin Cui ,  Raul E. Silvera

Inventor： Shimin Cui ,  Raul E. Silvera

IPC: G06F9/45 ,  G06F8/41

Abstract: An illustrative embodiment of a computer-implemented process for managing aliasing constraints, identifies an object to form an identified object, identifies a scope of the identified object to form an identified scope, and assigns a unique value to the identified object within the identified scope. The computer-implemented process further demarcates an entrance to the identified scope, demarcates an exit to the identified scope, optimizes the identified object using a property of the identified scope and associated aliasing information, tracks the identified object state to form tracked state information; and uses the tracked state information to update the identified object.

公开(公告)号：US20130019232A1

公开(公告)日：2013-01-17

申请号：US13545649

申请日：2012-07-10

Applicant: SHIMIN CUI ,  RAUL E. SILVERA

Inventor： SHIMIN CUI ,  RAUL E. SILVERA

IPC: G06F9/45

CPC classification number: G06F8/443

Abstract: An illustrative embodiment of a computer-implemented process for managing aliasing constraints, identifies an object to form an identified object, identifies a scope of the identified object to form an identified scope, and assigns a unique value to the identified object within the identified scope. The computer-implemented process further demarcates an entrance to the identified scope, demarcates an exit to the identified scope, optimizes the identified object using a property of the identified scope and associated aliasing information, tracks the identified object state to form tracked state information; and uses the tracked state information to update the identified object.

Abstract translation: 用于管理混叠约束的计算机实现的过程的说明性实施例，识别对象以形成识别的对象，识别所识别的对象的范围以形成所识别的范围，并且在所识别的范围内为所识别的对象分配唯一的值。 计算机实现的过程进一步划分到所识别的范围的入口，将出口划分为所识别的范围，使用所识别的范围和相关联的混叠信息的属性来优化所识别的对象，跟踪所识别的对象状态以形成跟踪状态信息; 并使用跟踪的状态信息来更新所识别的对象。

公开(公告)号：US08352684B2

公开(公告)日：2013-01-08

申请号：US12236188

申请日：2008-09-23

Applicant: Roch Georges Archambault ,  Shimin Cui ,  Chen Ding ,  Yaoqing Gao ,  Xiaoming Gu ,  Raul Esteban Silvera ,  Chengliang Zhang

Inventor： Roch Georges Archambault ,  Shimin Cui ,  Chen Ding ,  Yaoqing Gao ,  Xiaoming Gu ,  Raul Esteban Silvera ,  Chengliang Zhang

IPC: G06F12/00

CPC classification number: G06F12/123 ,  G06F2212/502

Abstract: Computer implemented method, system and computer usable program code for cache management. A cache is provided, wherein the cache is viewed as a sorted array of data elements, wherein a top position of the array is a most recently used position of the array and a bottom position of the array is a least recently used position of the array. A memory access sequence is provided, and a training operation is performed with respect to a memory access of the memory access sequence to determine a type of memory access operation to be performed with respect to the memory access. Responsive to a result of the training operation, a cache replacement operation is performed using the determined memory access operation with respect to the memory access.

Abstract translation: 计算机实现方法，系统和计算机可用程序代码进行缓存管理。 提供了缓存，其中高速缓存被视为数据元素的排序数组，其中阵列的顶部位置是阵列的最近使用的位置，并且阵列的底部位置是阵列的最近最近使用的位置 。 提供存储器访问序列，并且针对存储器访问序列的存储器访问执行训练操作，以确定要针对存储器访问执行的存储器访问操作的类型。 响应于训练操作的结果，使用关于存储器访问的确定的存储器访问操作来执行高速缓存替换操作。

公开(公告)号：US08332833B2

公开(公告)日：2012-12-11

申请号：US11757941

申请日：2007-06-04

Applicant: Roch Georges Archambault ,  Shimin Cui ,  Yaoqing Gao ,  Raul Esteban Silvera ,  Peng Zhao

Inventor： Roch Georges Archambault ,  Shimin Cui ,  Yaoqing Gao ,  Raul Esteban Silvera ,  Peng Zhao

IPC: G06F9/45

CPC classification number: G06F8/4441

Abstract: A computer implemented method for facilitating debugging of source code. The source code is scanned to identify a candidate region. A procedure control descriptor is generated, wherein the procedure control descriptor corresponds to the candidate region. The procedure control descriptor identifies, for the candidate region, a condition which, if true at runtime means that the candidate region can be specialized. Responsive to a determination during compile time that satisfaction of at least one condition will be known only at runtime, the procedure control descriptor is used to specialize the candidate region at compile time to create a first version of the candidate region for execution in a case where the condition is true and a second version of the candidate region for execution in a case where the condition is false, and further generate code to correctly select one of the first region and the second region at runtime.

Abstract translation: 一种用于促进源代码调试的计算机实现方法。 扫描源代码以识别候选区域。 生成过程控制描述符，其中过程控制描述符对应于候选区域。 程序控制描述符为候选区域识别条件，其在运行时为真，意味着候选区域可以是专门的。 在编译期间响应于在运行时仅满足至少一个条件的确定，过程控制描述符用于在编译时专门化候选区域，以在第一版本的候选区域中创建用于执行的候选区域， 条件为真，并且在条件为假的情况下用于执行的候选区域的第二版本，并且还在生成期间生成正确选择第一区域和第二区域中的一个的代码。

公开(公告)号：US20100162220A1

公开(公告)日：2010-06-24

申请号：US12343228

申请日：2008-12-23

Applicant: Shimin Cui ,  Raul Esteban Silvera

Inventor： Shimin Cui ,  Raul Esteban Silvera

IPC: G06F9/45

CPC classification number: G06F8/443

Abstract: Optimizing program code in a static compiler by determining the live ranges of variables and determining which live ranges are candidates for moving code from the use site to the definition site of source code. Live ranges for variables in a flow graph are determined. Selected live ranges are determined as candidates in which code will be moved from a use site within the source code to a definition site within the source code. Optimization opportunities within the source code are identified based on the code motion.

Abstract translation: 通过确定变量的生存范围并确定哪些生存范围是将代码从使用站点移动到源代码定义位置的候选者来优化静态编译器中的程序代码。 确定流程图中变量的活动范围。 选择的实时范围被确定为将代码从源代码中的使用站点移动到源代码中的定义站点的候选者。 基于代码运动来识别源代码中的优化机会。

公开(公告)号：US20100077153A1

公开(公告)日：2010-03-25

申请号：US12236188

申请日：2008-09-23

Applicant: Roch Georges Archambault ,  Shimin Cui ,  Chen Ding ,  Yaoqing Gao ,  Xiaoming Gu ,  Raul Esteban Silvera ,  Chengliang Zhang

Inventor： Roch Georges Archambault ,  Shimin Cui ,  Chen Ding ,  Yaoqing Gao ,  Xiaoming Gu ,  Raul Esteban Silvera ,  Chengliang Zhang

IPC: G06F12/08

CPC classification number: G06F12/123 ,  G06F2212/502

Abstract: Computer implemented method, system and computer usable program code for cache management. A cache is provided, wherein the cache is viewed as a sorted array of data elements, wherein a top position of the array is a most recently used position of the array and a bottom position of the array is a least recently used position of the array. A memory access sequence is provided, and a training operation is performed with respect to a memory access of the memory access sequence to determine a type of memory access operation to be performed with respect to the memory access. Responsive to a result of the training operation, a cache replacement operation is performed using the determined memory access operation with respect to the memory access.

Abstract translation: 计算机实现方法，系统和计算机可用程序代码进行缓存管理。 提供了缓存，其中高速缓存被视为数据元素的排序数组，其中阵列的顶部位置是阵列的最近使用的位置，并且阵列的底部位置是阵列的最近最近使用的位置 。 提供存储器访问序列，并且针对存储器访问序列的存储器访问执行训练操作，以确定要针对存储器访问执行的存储器访问操作的类型。 响应于训练操作的结果，使用关于存储器访问的确定的存储器访问操作来执行高速缓存替换操作。