公开(公告)号：US20240086329A1

公开(公告)日：2024-03-14

申请号：US18470553

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Vasileios Porpodas ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Wei-Yu Chen

IPC: G06F12/0862 ,  G06F8/41 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F12/0862 ,  G06F8/41 ,  G06F8/4442 ,  G06F9/30047 ,  G06F12/0875 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/502 ,  G06F2212/602 ,  G06F2212/6028

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

公开(公告)号：US11842049B2

公开(公告)日：2023-12-12

申请号：US17465025

申请日：2021-09-02

Applicant: Amazon Technologies, Inc.

Inventor： Munif M. Farhan ,  Phyllis Ng ,  Darin Lee Frink ,  Nafea Bshara

IPC: G06F3/06 ,  G06F12/0866 ,  G06F12/0868 ,  G06F11/34 ,  G06F12/0871 ,  G06F12/121

CPC classification number: G06F3/061 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0676 ,  G06F3/0679 ,  G06F11/34 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/224 ,  G06F2212/313 ,  G06F2212/502 ,  G06F2212/601

Abstract: Technologies are provided for dynamically changing a size of a cache region of a storage device. A storage device controller writes data to the cache region of the storage device using a particular storage format. The storage device controller then migrates the cached data to a storage region of the device, where the data is written using a different storage format. A dynamic cache manager monitors input and output activity for the storage device and dynamically adjusts a size of the cache region to adapt to changes in the input and/or output activity. The dynamic cache manager can also adjust a size of the storage region. The storage device controller can automatically detect that the storage device has dynamic cache support and configure the storage device by creating the cache region and the storage region on the device.

公开(公告)号：US11803476B2

公开(公告)日：2023-10-31

申请号：US17210867

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Vasileios Porpodas ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Wei-Yu Chen

IPC: G06F12/0862 ,  G06F12/0875 ,  G06F9/30 ,  G06F8/41

CPC classification number: G06F12/0862 ,  G06F8/41 ,  G06F8/4442 ,  G06F9/30047 ,  G06F12/0875 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/502 ,  G06F2212/602 ,  G06F2212/6028

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

公开(公告)号：US20190121423A1

公开(公告)日：2019-04-25

申请号：US16223818

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F12/084 ,  G06F12/0802 ,  G06F1/28 ,  G06F12/0864 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20190121422A1

公开(公告)日：2019-04-25

申请号：US16223794

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F12/084 ,  G06F12/0802 ,  G06F1/28 ,  G06F12/0864 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20180276134A1

公开(公告)日：2018-09-27

申请号：US15467423

申请日：2017-03-23

Applicant: International Business Machines Corporation

Inventor： Giovanni Cherubini ,  Yusik Kim ,  Mark A. Lantz ,  Vinodh Venkatesan

IPC: G06F12/0888 ,  G06N7/00

CPC classification number: G06F12/0888 ,  G06F12/08 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/502 ,  G06F2212/6026 ,  G06N7/005

Abstract: A computer-implemented method is provided for managing digital datasets stored on a multi-tiered storage system that includes several tiers of storage, the datasets likely to be accessed by one or more applications interacting with the storage system. The method includes monitoring an access history of datasets accessed by the one or more applications; and while monitoring the access history: computing probabilities of access, by the one or more applications, of the datasets stored on the storage system according to metadata associated to given datasets as identified in the monitored access history; and based on the computed probabilities of access, selecting one or more of the datasets to be moved across the tiers. Related storage systems and computer program products are also provided.

公开(公告)号：US20180239717A1

公开(公告)日：2018-08-23

申请号：US15832804

申请日：2017-12-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shrirang S. Bhagwat ,  Pankaj Deshpande ,  Rahul M. Fiske ,  Ashwin Joshi ,  Subhojit Roy

IPC: G06F12/126

CPC classification number: G06F12/126 ,  G06F12/0862 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/154 ,  G06F2212/263 ,  G06F2212/311 ,  G06F2212/502 ,  G06F2212/6028 ,  G06F2212/70

Abstract: Cache prefetching in offloaded data transfer (ODX) processes. A populate token command is received to initiate a copy offload operation. Responsive to receiving the populate token command, a cache of a data storage system in a storage area network environment is instructed to prefetch data in accordance with the populate token command and complete an offloaded read request. Responsive to determining that a write using token command is not received within a specified time duration, the prefetched data stored in the cache is evicted.

公开(公告)号：US20180225043A1

公开(公告)日：2018-08-09

申请号：US15875048

申请日：2018-01-19

Applicant: NEC Corporation

Inventor： Naoshi ORIHARA

IPC: G06F3/06 ,  G06F9/50 ,  G06F12/0871 ,  G06F9/455

CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/45558 ,  G06F9/5016 ,  G06F12/0871 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/263 ,  G06F2212/284 ,  G06F2212/314 ,  G06F2212/502 ,  G06F2212/6042

Abstract: A disk control device includes a hypervisor, a cache access measurement unit, and a distribution determination unit. The cache access measurement unit measures a characteristic value of a logical disk by analyzing an access pattern to the logical disk by a cache memory. The distribution determination unit selects one of a plurality of virtual computers including the cache memory associated with the measured characteristic value. The hypervisor activates the virtual computer selected by the distribution determination unit and switches a forwarding destination of an input-output request to the logical disk to the virtual computer selected by the distribution determination unit.

公开(公告)号：US20180203800A1

公开(公告)日：2018-07-19

申请号：US15746465

申请日：2015-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Alexandros Daglis ,  Paolo Fraboschi ,  Qiong Cai ,  Gary Gostin

IPC: G06F12/0817

CPC classification number: G06F12/0817 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/1441 ,  G06F12/1458 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/502

Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

公开(公告)号：US20180189062A1

公开(公告)日：2018-07-05

申请号：US15396177

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Sara S. Baghsorkhi ,  Christos Margiolas

IPC: G06F9/30 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F9/3016 ,  G06F3/06 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30058 ,  G06F9/30101 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F12/1009 ,  G06F12/1027 ,  G06F15/76 ,  G06F2212/205 ,  G06F2212/502

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a source memory address information, and is to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result to indicate whether a logical memory address corresponding to the source memory address information is in a persistent memory. Other processors, methods, systems, and instructions are disclosed.