公开(公告)号：US07873777B2

公开(公告)日：2011-01-18

申请号：US11698133

申请日：2007-01-26

Applicant: Shin-wook Kang

Inventor： Shin-wook Kang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0607 ,  G06F2212/7203

Abstract: Provided are a multi-channel flash memory system capable of increasing the overall bandwidth by using a plurality of flash memory chips, and a programming method performed in the flash memory system. The flash memory system includes: a plurality of channel units each including at least two flash memory chips, a control unit which controls the flash memory chips, and a buffer unit which stores external data; and a host interface unit which transmits data separated according to the number of the channel units and transmitted by a host to the buffer units of the channel units, wherein the control unit records the data stored in the buffer unit into the at least two flash memory chips.

Abstract translation: 提供了能够通过使用多个闪速存储器芯片来增加总体带宽的多通道快闪存储器系统，以及在闪速存储器系统中执行的编程方法。 闪存系统包括：多个通道单元，每个通道单元包括至少两个闪存芯片，控制闪存芯片的控制单元和存储外部数据的缓冲器单元; 以及主机接口单元，其发送根据所述信道单元的数量分离并由主机发送到所述信道单元的缓冲器单元的数据，其中所述控制单元将存储在所述缓冲器单元中的数据记录到所述至少两个闪存中 筹码

公开(公告)号：US20080301381A1

公开(公告)日：2008-12-04

申请号：US12099287

申请日：2008-04-08

Applicant: Dong-woo LEE ,  Houng-sog Min ,  Shin-wook Kang ,  Hyang-suk Park ,  Seong-hun Jeong ,  Sang-seob Shin ,  Hye-lime Jeong

Inventor： Dong-woo LEE ,  Houng-sog Min ,  Shin-wook Kang ,  Hyang-suk Park ,  Seong-hun Jeong ,  Sang-seob Shin ,  Hye-lime Jeong

IPC: G06F12/00

CPC classification number: G06F13/28 ,  G06F3/0601 ,  G06F2003/0692

Abstract: A method and device for controlling commands used for a flash memory are provided. The method includes, substantially reducing usage of a central processing unit (CPU) and a bus, when controlling the flash memory, by receiving information on at least one command currently stored in a system memory, receiving a command represented by the received information from the system memory, and generating an interrupt representing that all the commands are received, when receiving of substantially all the commands represented by the received information is completed.

Abstract translation: 提供了一种用于控制用于闪速存储器的命令的方法和装置。 该方法包括：通过接收当前存储在系统存储器中的至少一个命令的信息来控制闪速存储器时，大大减少中央处理单元（CPU）和总线的使用，接收来自 并且当接收到基本上所有由所接收的信息表示的命令完成时，产生表示接收到所有命令的中断。

公开(公告)号：US07589999B2

公开(公告)日：2009-09-15

申请号：US11713638

申请日：2007-03-05

Applicant: Seong-hun Jeong ,  Houng-sog Min ,  Dong-woo Lee ,  Shin-wook Kang ,  Hyang-suk Park

Inventor： Seong-hun Jeong ,  Houng-sog Min ,  Dong-woo Lee ,  Shin-wook Kang ,  Hyang-suk Park

IPC: G11C11/34

CPC classification number: G11C16/102 ,  G11C2216/14

Abstract: A method and apparatus are provided for programming a non-volatile data storage device, in which a fast write operation can be performed using a plurality of page buffers included in the non-volatile data storage device when the write operation is performed in a way of using interleaving for each channel in a multi-channel system using a plurality of non-volatile data storage devices. The method includes programming data in a memory cell array included in the non-volatile data storage device using a page buffer selected from among a plurality of page buffers included in the non-volatile data storage device and performing a setup operation for loading data using another page buffer, which is different from the page buffer selected during the programming.

Abstract translation: 提供了一种用于对非易失性数据存储装置进行编程的方法和装置，其中当以非法数据存储装置的方式执行写入操作时，可以使用包括在非易失性数据存储装置中的多个页缓冲器执行快速写入操作 使用多个非易失性数据存储设备在多信道系统中对每个信道进行交织。 该方法包括使用从非易失性数据存储装置中包括的多个页缓冲器中选择的页缓冲器来编程包括在非易失性数据存储装置中的存储单元阵列中的数据，并执行用于使用另一个装载数据加载数据的设置操作 页面缓冲区，与编程期间选择的页面缓冲区不同。

公开(公告)号：US20090049464A1

公开(公告)日：2009-02-19

申请号：US12029675

申请日：2008-02-12

Applicant: Shin-wook KANG

Inventor： Shin-wook KANG

IPC: H04N7/16 ,  H04N7/173

CPC classification number: H04N7/17318 ,  G06Q30/06 ,  H04N21/4184 ,  H04N21/42692 ,  H04N21/4334 ,  H04N21/44204 ,  H04N21/47202 ,  H04N21/47815 ,  H04N21/8355

Abstract: Users of a method and apparatus to purchase (e.g., rent or buy) contents using a portable storage medium, via a network or the like. Contents purchased using embodiments of a method and apparatus may be developed to be automatically deleted or to be non-reproducible after being reproduced one time or after a predetermined period. Accordingly, users do not need to return borrowed or purchased contents. Also an owner of a contents rental shop may prevent contents from being unfairly reproduced. Further, user inconvenience due to the conventional manner in which users have to memorize information related to the contents and visit a rental shop to obtain desired contents may be avoided or decreased. Portable storage mediums or network resources of exemplary methods and apparatuses may be repeatedly used (e.g., without limitation), and thus may contribute to the saving of resources.

Abstract translation: 使用便携式存储介质经由网络等购买（例如，租赁或购买）内容的方法和装置的用户。 可以开发使用方法和装置的实施例购买的内容，以便在被再现一次或在预定时间段之后被自动删除或不可重现。 因此，用户不需要返回借用或购买的内容。 内容租赁店的所有者也可能阻止内容被不公平地复制。 此外，可以避免或减少由于用户必须记住与内容相关的信息并访问租赁商店以获得期望的内容的常规方式的用户不便。 示例性方法和装置的便携式存储介质或网络资源可以重复使用（例如但不限于），并且因此可以有助于节省资源。

公开(公告)号：US20070288688A1

公开(公告)日：2007-12-13

申请号：US11698133

申请日：2007-01-26

Applicant: Shin-wook Kang

Inventor： Shin-wook Kang

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F12/0607 ,  G06F2212/7203

Abstract: Provided are a multi-channel flash memory system capable of increasing the overall bandwidth by using a plurality of flash memory chips, and a programming method performed in the flash memory system. The flash memory system includes: a plurality of channel units each including at least two flash memory chips, a control unit which controls the flash memory chips, and a buffer unit which stores external data; and a host interface unit which transmits data separated according to the number of the channel units and transmitted by a host to the buffer units of the channel units, wherein the control unit records the data stored in the buffer unit into the at least two flash memory chips.

Abstract translation: 提供了能够通过使用多个闪速存储器芯片来增加总体带宽的多通道快闪存储器系统，以及在闪速存储器系统中执行的编程方法。 闪存系统包括：多个通道单元，每个通道单元包括至少两个闪存芯片，控制闪存芯片的控制单元和存储外部数据的缓冲器单元; 以及主机接口单元，其发送根据所述信道单元的数量分离并由主机发送到所述信道单元的缓冲器单元的数据，其中所述控制单元将存储在所述缓冲器单元中的数据记录到所述至少两个闪存中 筹码

公开(公告)号：US20060080492A1

公开(公告)日：2006-04-13

申请号：US11142463

申请日：2005-06-02

Applicant: Sang-ik Choi ,  Shin-wook Kang ,  Hyang-suk Park

Inventor： Sang-ik Choi ,  Shin-wook Kang ,  Hyang-suk Park

IPC: G06F13/36

CPC classification number: G06F13/405 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a bridge for interfacing buses within an embedded system. There is provided a method of interfacing a first bus and a second bus operating at different speeds, the method includes counting a match value assigned to a predetermined peripheral device among peripheral devices connected to the second bus for each cycle of a clock signal received from the first bus, and keeping a read state or a write state for the predetermined peripheral device by continuously outputting a read signal or a write signal for the predetermined peripheral device to the second bus, during the counting of the match value. According to the present invention, it is not necessary to operate depending on a peripheral device operating at the lowest speed among peripheral devices, and not necessary to add wrappers to the peripheral devices, by employing the AHB-to-ISA bridge variably adjusting the output times of output signals to an ISA bus.

Abstract translation: 本发明涉及一种用于在嵌入式系统内接口总线的桥接器。 提供了一种接口第一总线和以不同速度工作的第二总线的方法，该方法包括对从第二总线连接到第二总线的外围设备分配给与从第二总线接收的时钟信号的每个周期相匹配的匹配值进行计数 并且在匹配值的计数期间，通过连续地向第二总线输出用于预定的外围设备的读取信号或写入信号，为预定的外围设备保持读取状态或写入状态。 根据本发明，不需要根据外围设备中以最低速度操作的外围设备进行操作，并且不需要通过使用可变地调整输出的AHB-ISA桥接器向外围设备添加封装 输出信号到ISA总线的次数。

公开(公告)号：US20050182868A1

公开(公告)日：2005-08-18

申请号：US11059467

申请日：2005-02-16

Applicant: Shin-wook Kang

Inventor： Shin-wook Kang

IPC: G06F12/02 ,  G06F13/00 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1018 ,  G11C7/22

Abstract: An apparatus and method for controlling access to a memory to minimize a latency in a bus system when there is a wrapping burst request from a bus. The apparatus includes a first detecting unit detecting a burst length in a wrapping burst instruction received from the bus master when the command received from the bus master is the wrapping burst instruction, a second detecting unit detecting in the received wrapping burst instruction a start address of a region of the memory to be accessed when the command received from the bus master is the wrapping burst instruction, and a finite state machine (FSM) detecting an address to be wrapped based on the detection results of the first and the second detecting units and generating signals for controlling the memory to output a CAS command of the address to be wrapped.

Abstract translation: 一种用于控制对存储器的访问的装置和方法，以便当存在来自总线的环绕突发请求时，使总线系统中的等待时间最小化。 该装置包括第一检测单元，当从总线主机接收到的命令是包绕脉冲串指令时，从总线主机接收到的打包脉冲串指令中检测脉冲串长度;第二检测单元，检测接收到的环绕脉冲串指令的起始地址 当从总线主机接收到的命令是包络突发指令时，要访问的存储器的区域，以及基于第一和第二检测单元的检测结果来检测要包装的地址的有限状态机（FSM），以及 产生用于控制存储器的信号，以输出要包装的地址的CAS命令。

公开(公告)号：US09071849B2

公开(公告)日：2015-06-30

申请号：US13082929

申请日：2011-04-08

Applicant: Jae-won Yoon ,  Sung-bum Park ,  Hae-young Jun ,  Shin-wook Kang ,  Dai-woong Choi

Inventor： Jae-won Yoon ,  Sung-bum Park ,  Hae-young Jun ,  Shin-wook Kang ,  Dai-woong Choi

IPC: H04N19/00 ,  H04N19/593

CPC classification number: H04N19/593

Abstract: A method and apparatus for generating video packets and a method and apparatus for restoring video are provided. The method of generating video packets includes: generating at least one pixel block consisting of at least one reference pixel and a plurality of neighboring pixels adjacent to the at least one reference pixel from pixels of a video frame; replacing pixel values of the neighboring pixels in the at least one pixel block with pixel difference values, which are difference values between a pixel value of one of pixels adjacent to the neighboring pixels and the pixel values of the neighboring pixels; generating packets so that a pixel value of the at least one reference pixel and the pixel difference values of the neighboring pixels are allocated to different packets according to positions of the pixels; and performing entropy coding of some of the packets including the pixel difference values of the neighboring pixels.

Abstract translation: 提供了一种用于产生视频分组的方法和装置以及用于恢复视频的方法和装置。 产生视频分组的方法包括：从视频帧的像素生成由与至少一个参考像素相邻的至少一个参考像素和多个相邻像素组成的至少一个像素块; 用像素差值代替所述至少一个像素块中的相邻像素的像素值，所述像素差值是与相邻像素相邻的一个像素的像素值与相邻像素的像素值之间的差值; 生成分组，使得根据像素的位置将所述至少一个参考像素的像素值和相邻像素的像素差值分配给不同的分组; 并执行包括相邻像素的像素差值的一些分组的熵编码。

公开(公告)号：US20110274177A1

公开(公告)日：2011-11-10

申请号：US13103578

申请日：2011-05-09

Applicant: Sung-bum PARK ,  Jae-won YOON ,  Hae-young JUN ,  Shin-wook KANG ,  Dai-woong CHOI ,  Huai-rong SHAO

Inventor： Sung-bum PARK ,  Jae-won YOON ,  Hae-young JUN ,  Shin-wook KANG ,  Dai-woong CHOI ,  Huai-rong SHAO

IPC: H04N7/26

CPC classification number: H04N19/182 ,  H04N19/105 ,  H04N19/124 ,  H04N19/176 ,  H04N19/184 ,  H04N19/593 ,  H04N19/91

Abstract: A method and apparatus for processing a video frame is provided. The method includes dividing the video frame into pixel blocks each including a reference pixel; calculating difference values between the reference pixel and pixels neighboring the reference pixel; converting the calculated difference values into values that belong to a bit depth range; and performing entropy coding by using the converted difference values as symbols.

Abstract translation: 提供了一种用于处理视频帧的方法和装置。 该方法包括将视频帧划分为每个包括参考像素的像素块; 计算参考像素和与参考像素相邻的像素之间的差值; 将计算的差值转换为属于比特深度范围的值; 以及通过使用转换的差值作为符号来执行熵编码。

公开(公告)号：US07765359B2

公开(公告)日：2010-07-27

申请号：US11730800

申请日：2007-04-04

Applicant: Shin-wook Kang ,  Dong-woo Lee

Inventor： Shin-wook Kang ,  Dong-woo Lee

IPC: G06F12/00

CPC classification number: G11C16/10

Abstract: Provided are a flash memory system and a programming method performed in the flash memory system. The flash memory system includes a buffer unit including a plurality of buffers, and temporarily storing data transmitted by a host; a plurality of channel units each including at least one flash memory chip that includes a plurality of memory cell arrays; and a control unit which controls the data stored in the buffer unit to be sequentially transmitted to the channel units and the transmitted data to be recorded to the memory cell arrays of the flash memory chips in the channel units.

Abstract translation: 提供了一种在闪存系统中执行的闪存系统和编程方法。 闪速存储器系统包括：缓冲单元，包括多个缓冲器，并临时存储主机发送的数据; 多个通道单元，每个通道单元包括至少一个包括多个存储单元阵列的闪存芯片; 以及控制单元，其将存储在缓冲器单元中的数据顺序地发送到频道单元，并将发送的数据记录到频道单元中的闪存芯片的存储单元阵列。