摘要:
A method, apparatus, computer medium, and other embodiments for motion estimation and compensation processing of video and image signals are described. Within a sequence of frames, block-based differences are taken between frames to exploit redundancies between pictures by taking a matchblock from the current picture and by determining a spatial offset in a corresponding reference picture which signifies a good prediction of where the current macroblock can be found. Multi-level motion estimation is performed in three stages to refine the resolution of the motion vector with reduced computational bandwidth. First, a matchblock from a reference frame is decomposed equally into several sub-matchblocks, each of which is searched in parallel over a search area decomposed into sub-blocks by a similar factor so as to determine a preliminary motion vector in the reference picture. Second, a full size matchblock is then searched over a refined search area using the preliminary motion vector to determine an intermediate motion vector, so as to refine the resolution of the preliminary motion vector. Third, fractional-pixel searching is then performed on the matchblock and the intermediate motion vector to determine a final motion vector having an even higher resolution associated with the best motion vector to be used in predicting the current macroblock. In one embodiment, a processor-based motion estimation and compensation cell array enables contemporaneous and independent loading and processing operations in parallel.
摘要:
Embodiments of the present invention provide methods and associated architecture of accuracy adaptive and scalable vector graphics rendering including rendering a graphic comprising a plurality of line segments by processing each of the plurality of line segments in a first pass, and processing each of a plurality of pixels through which the plurality of line segments pass in a second pass, automatically detecting one or more rendering errors of the graphic, and correcting the one or more rendering errors. Other embodiments may be described and/or claimed.
摘要:
A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.
摘要:
The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.
摘要:
A method, apparatus, computer medium, and other embodiments for synchronizing control of one or more devices at predetermined times are described. A host scheduler loads a to-do list of predetermined events and corresponding time-tags into memory and broadcasts scheduled events to the devices to cause activation of the events on intended devices.
摘要:
The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.
摘要:
A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described.
摘要:
A method, apparatus, computer medium, and other embodiments for motion estimation and compensation processing of video and image signals are described. Within a sequence of frames, block-based differences are taken between frames to exploit redundancies between pictures by taking a matchblock from the current picture and by determining a spatial offset in a corresponding reference picture which signifies a good prediction of where the current macroblock can be found. Multi-level motion estimation is performed in three stages to refine the resolution of the motion vector with reduced computational bandwidth. First, a matchblock from a reference frame is decomposed equally into several sub-matchblocks, each of which is searched in parallel over a search area decomposed into sub-blocks by a similar factor so as to determine a preliminary motion vector in the reference picture. Second, a full size matchblock is then searched over a refined search area using the preliminary motion vector to determine an intermediate motion vector, so as to refine the resolution of the preliminary motion vector. Third, fractional-pixel searching is then performed on the matchblock and the intermediate motion vector to determine a final motion vector having an even higher resolution associated with the best motion vector to be used in predicting the current macroblock. In one embodiment, a processor-based motion estimation and compensation cell array enables contemporaneous and independent loading and processing operations in parallel.
摘要:
A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described.
摘要:
A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.