公开(公告)号：US06609209B1

公开(公告)日：2003-08-19

申请号：US09474461

申请日：1999-12-29

Applicant: Vivek Tiwari ,  Vinod Sharma ,  Sivakumar Makineni ,  Suri B. Medapati

Inventor： Vivek Tiwari ,  Vinod Sharma ,  Sivakumar Makineni ,  Suri B. Medapati

IPC: G06F132

CPC classification number: G06F9/3869 ,  G06F1/3228 ,  G06F1/3243 ,  G06F9/3861 ,  Y02D10/152

Abstract: A processor includes a pipeline having first and second stages and a shift register having first and second latches. An interface circuit is used to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.

Abstract translation: 处理器包括具有第一和第二级的管线和具有第一和第二锁存器的移位寄存器。 接口电路用于至少部分地基于要存储在第一和第二锁存器中的第一和第二位来从时钟信号线向第一和第二级提供时钟信号。

公开(公告)号：US5696711A

公开(公告)日：1997-12-09

申请号：US577726

申请日：1995-12-22

Applicant: Sivakumar Makineni

Inventor： Sivakumar Makineni

IPC: G06F7/57 ,  G06F7/38

CPC classification number: G06F7/483 ,  G06F7/49957

Abstract: An apparatus and method for performing variable precision floating point rounding operations is provided that accomplishes rounding of a number that is faster, less complex and requires less hardware than conventional devices. The apparatus and method provides for a single uniform incrementer located at the zero position that can add a logic 1 to that position. After the Round, Guard and Sticky bits are produced, logic 1s are inserted in the bit positions to the right of the significant bits of the result with a check unit. The check unit then outputs the intermediate result to an incrementer and a zero-out unit. The incrementer adds a 1 to the zero position and the carry function of the incrementer by operation ripples through the series of 1s up to the rightmost position of the resultant mantissa leaving a trail of zeroes behind producing a first output. Finally, a multiplexer is provided to choose between the first output and the second output as the final result.

Abstract translation: 提供了一种用于执行可变精度浮点舍入操作的装置和方法，其实现与传统设备相比更快，更不复杂并且需要更少硬件的数字的舍入。 装置和方法提供位于零位置的单个均匀加法器，其可以将逻辑1添加到该位置。 在产生Round，Guard和Sticky位之后，逻辑1被插入到具有检查单元的结果的有效位右侧的位位置中。 然后，检查单元将中间结果输出到增量器和零输出单元。 增量器通过一系列1s的操作波形将加法器的零位和进位功能加1，直到得到的尾数的最右边位置留下零的轨迹，产生第一个输出。 最后，提供多路复用器作为最终结果在第一输出和第二输出之间进行选择。