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1.发明授权Method and apparatus for reducing the power consumed by a processor by gating the clock signal to pipeline stages 有权用于通过将时钟信号门控到流水线级来降低处理器消耗的功率的方法和装置公开(公告)号：US06609209B1
公开(公告)日：2003-08-19
申请号：US09474461
申请日：1999-12-29
IPC分类号： G06F132
CPC分类号： G06F9/3869 , G06F1/3228 , G06F1/3243 , G06F9/3861 , Y02D10/152
摘要： A processor includes a pipeline having first and second stages and a shift register having first and second latches. An interface circuit is used to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.
摘要翻译： 处理器包括具有第一和第二级的管线和具有第一和第二锁存器的移位寄存器。 接口电路用于至少部分地基于要存储在第一和第二锁存器中的第一和第二位来从时钟信号线向第一和第二级提供时钟信号。
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公开(公告)号：US07035891B2
公开(公告)日：2006-04-25
申请号：US10228432
申请日：2002-08-27
IPC分类号： G06F11/16
CPC分类号： G06F11/0751 , G06F11/0721
摘要： A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.
摘要翻译： 提供了一种方法和系统，用于在不使用冗余逻辑的情况下执行整数加减运算的软错误检测。 对于整数加法和减法，补偿逻辑利用算术逻辑单元（ALU）结果和操作数产生补偿值。 补偿值由验证逻辑针对预定值确认，以确定是否发生软错误。 这种补偿逻辑和验证逻辑对整数操作数和ALU产生的结果无冗余的进位传播硬件进行操作。
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公开(公告)号：US5880985A
公开(公告)日：1999-03-09
申请号：US735058
申请日：1996-10-18
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F2207/382
摘要： In order to multiply operands of different binary lengths using a common combined array, for example to do both 8 bit by 8 bit and 16 bit by 16 bit multiplications, 2.sup.m-1 multiplications are performed, where m is equal to the number of different bit lengths it is desired to multiply. For example, where 8.times.8 bit and 16.times.16 bit multiplications are done, 2 different multiplications are done. Each multiplication is an n.times.n/2.sup.m-1 multiplication, e.g., a 16.times.8 bit multiplication. Sign correction is performed by adding a correction vector or by modifying one of the partial products. The results of the multiplications are added together to obtain a 2 n bit result. Groups of bits from said 2 n result are selected depending on the length of the operands being multiplied.
摘要翻译： 为了使用公共组合阵列对不同二进制长度的操作数进行乘法运算，例如进行8位乘8位和16位乘16位乘法运算，执行2m-1乘法，其中m等于不同位数 希望乘以长度。 例如，在完成8×8位和16×16位乘法的情况下，完成2次不同的乘法。 每个乘法是nxn / 2m-1乘法，例如16×8位乘法。 通过添加校正矢量或通过修改部分乘积之一来执行符号校正。 将乘法的结果相加在一起以获得2 n位结果。 来自所述2n结果的比特组根据被乘以的操作数的长度来选择。
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4.发明授权Apparatus and method for performing variable precision floating point rounding operations 失效用于执行可变精度浮点舍入操作的装置和方法
公开(公告)号：US5696711A
公开(公告)日：1997-12-09
申请号：US577726
申请日：1995-12-22
申请人： Sivakumar Makineni
发明人： Sivakumar Makineni
CPC分类号： G06F7/483 , G06F7/49957
摘要： An apparatus and method for performing variable precision floating point rounding operations is provided that accomplishes rounding of a number that is faster, less complex and requires less hardware than conventional devices. The apparatus and method provides for a single uniform incrementer located at the zero position that can add a logic 1 to that position. After the Round, Guard and Sticky bits are produced, logic 1s are inserted in the bit positions to the right of the significant bits of the result with a check unit. The check unit then outputs the intermediate result to an incrementer and a zero-out unit. The incrementer adds a 1 to the zero position and the carry function of the incrementer by operation ripples through the series of 1s up to the rightmost position of the resultant mantissa leaving a trail of zeroes behind producing a first output. Finally, a multiplexer is provided to choose between the first output and the second output as the final result.
摘要翻译： 提供了一种用于执行可变精度浮点舍入操作的装置和方法，其实现与传统设备相比更快，更不复杂并且需要更少硬件的数字的舍入。 装置和方法提供位于零位置的单个均匀加法器，其可以将逻辑1添加到该位置。 在产生Round，Guard和Sticky位之后，逻辑1被插入到具有检查单元的结果的有效位右侧的位位置中。 然后，检查单元将中间结果输出到增量器和零输出单元。 增量器通过一系列1s的操作波形将加法器的零位和进位功能加1，直到得到的尾数的最右边位置留下零的轨迹，产生第一个输出。 最后，提供多路复用器作为最终结果在第一输出和第二输出之间进行选择。
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公开(公告)号：US06292886B1
公开(公告)日：2001-09-18
申请号：US09169865
申请日：1998-10-12
IPC分类号： G06F1716
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/3893
摘要： A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packed operand into an unpacked operand for processing by the first execution unit. Another SIMD operand is processed by the vector execution unit.
摘要翻译： 用于以打包数据格式处理SIMD操作数的系统包括标量FMAC和通过操作数传送模块耦合到寄存器文件的向量FMAC。 对于向量操作，操作数传送模块位将打包操作数的SIMD操作数转换为解包操作数，以供第一执行单元处理。 另一个SIMD操作数由向量执行单元处理。
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6.发明授权Apparatus for bypassing intermediate results from a pipelined floating point unit to multiple successive instructions 失效用于将流水线浮点单元的中间结果旁路到多个连续指令的装置
公开(公告)号：US5996065A
公开(公告)日：1999-11-30
申请号：US831473
申请日：1997-03-31
申请人： Sivakumar Makineni , Brian L. Hughes , Sunhyuk Kimn , Michael Chow , Suri Babu Medapati , Albert Lo
发明人： Sivakumar Makineni , Brian L. Hughes , Sunhyuk Kimn , Michael Chow , Suri Babu Medapati , Albert Lo
CPC分类号： G06F9/3875 , G06F7/483 , G06F9/3826 , G06F2207/3884 , G06F7/49947
摘要： A microprocessor having a pipelined floating point unit operable to bypass pre-rounded results at clock cycle i and provide the pre-rounded results as an operand for a second instruction at clock cycle i+2. In one embodiment, the pipelined execution unit includes at least a first execution step at clock cycle i, and a second execution step at a clock cycle i+1 and clock cycle i+2. The unit includes a bypass leading from the first execution step at clock cycle i, however, there is no bypass leading from the second execution step at clock cycle i+1. The bypass carries the pre-rounded results from the end of the first execution step to the front end of the pipeline via a latched data path which delays the pre-rounded result one clock cycle.
摘要翻译： 具有流水线浮点单元的微处理器，其可操作以在时钟周期i旁路预翻转结果，并将预翻转结果提供为在时钟周期i + 2处的第二指令的操作数。 在一个实施例中，流水线执行单元至少包括在时钟周期i的第一执行步骤和在时钟周期i + 1和时钟周期i + 2的第二执行步骤。 该单元包括在时钟周期i从第一执行步骤引出的旁路，然而，在时钟周期i + 1处没有从第二执行步骤引出的旁路。 旁路通过锁存的数据路径将从第一执行步骤结束的前一轮结果传送到流水线的前端，该锁存数据路径延迟了一个时钟周期的预循环结果。
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公开(公告)号：US5793654A
公开(公告)日：1998-08-11
申请号：US719835
申请日：1996-09-30
CPC分类号： G06F5/012
摘要： A saturating alignment shifter for use in the multiply and accumulate unit in a floating point arithmetic unit of a microprocessor that mimics the ideal model of an infinitely wide shifter. A saturation alignment shifter is provided that, in the case of the operation of A*B.+-.C, saturates at a predetermined shifting increment and, in the case where the mantissa of C is saturated, places the mantissa C in the left most significant bits. After adding C to A*B in a summation unit, the mantissa of A*B ends up in the right most significant bits and a single intervening bit, termed the bubble bit, remains between the mantissa of C and the mantissa of A*B. The bubble bit acts to mimic any intervening bits that would have occurred in the case of an ideal infinitely wide shifter. The new shifter eliminates hardware required for special cases and treats all operations with a single alignment shifter giving a system that is faster and more simple than conventional systems.
摘要翻译： 一种饱和对准移位器，用于微处理器的浮点算术单元中的乘法和累积单元，该微处理器模拟无限宽移位器的理想模型。 提供饱和对准移位器，在A * B +/- C的操作的情况下，以预定的移动增量饱和，并且在C的尾数饱和的情况下，将尾数C置于最左侧 位。 在求和单元中向A * B添加C之后，A * B的尾数最终在最右边的最高有效位，并且称为气泡位的单个中间位保留在C的尾数与A * B的尾数之间 。 气泡位用于模拟在理想的无限宽移位器的情况下将发生的任何中间位。 新的移位器消除了特殊情况下所需的硬件，并使用单个对准移位器处理所有操作，给出比传统系统更快更简单的系统。
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8.发明授权
公开(公告)号：US5771183A
公开(公告)日：1998-06-23
申请号：US672678
申请日：1996-06-28
申请人： Sivakumar Makineni
发明人： Sivakumar Makineni
CPC分类号： G06F7/485 , G06F5/012 , G06F7/49952
摘要： Provided is a multi-stage shifter for use in both alignment and normalization shifters that provides faster implementation of the shifting process, requires less hardware and is less complex. One embodiment of the present invention provides a shift controller generating shift controller signals and a multi-stage normalization shifter having distinct multiple stages, coupled to a shift controller and receiving a number for normalization. The multi-stage shifter shifts the input number at predetermined increments at each stage and producing a sticky bit output at each stage that participates in the final sticky bit. These sticky bit outputs are ORed together to produce the final sticky bit. The present invention provides for production of the sticky bit with less hardware without sacrificing performance.
摘要翻译： 提供了一种用于对准和归一化移位器的多级移位器，其提供更快地实现移位过程，需要较少的硬件并且不太复杂。 本发明的一个实施例提供了一种换档控制器，其产生换档控制器信号和具有不同多级的多级归一化换档器，其耦合到换档控制器并接收用于归一化的数字。 多级移位器在每个阶段以预定增量移动输入数，并在参与最终粘性位的每个阶段产生粘性位输出。 这些粘性位输出被合并在一起以产生最终的粘性位。 本发明提供了在不牺牲性能的情况下以更少的硬件生产粘性位。
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公开(公告)号：US06378067B1
公开(公告)日：2002-04-23
申请号：US09170132
申请日：1998-10-12
申请人： Roger Golliver , Gautam Doshi , Sivakumar Makineni
发明人： Roger Golliver , Gautam Doshi , Sivakumar Makineni
IPC分类号： G06F948
CPC分类号： G06F9/3861 , G06F7/49905 , G06F9/30036
摘要： A method and apparatus to handle exceptions. The method receives and prioritizes exceptions resulting from executing an instruction on different elements of an operand. The exceptions are reported to an interrupt service register which communicates the exceptions to an exception handler to effectively process the exceptions.
摘要翻译： 一种处理异常的方法和装置。 该方法接收并对来自对操作数的不同元素执行指令的异常进行优先排序。 异常报告给一个中断服务寄存器，它将异常传递给异常处理程序，以有效地处理异常。
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10.发明授权Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations 有权用于设置与在SIMD操作中归一化的打包浮点型操作数的每个组件相关联的位的方法公开(公告)号：US06321327B1
公开(公告)日：2001-11-20
申请号：US09223457
申请日：1998-12-30
IPC分类号： G06F738
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/30192
摘要： A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.
摘要翻译： 提供了一种用于将打包的浮点操作数加载到具有一个或多个相关隐含位的寄存器文件条目中的方法。 打包浮点操作数包括多个组件操作数。 每个组件操作数的有效位和指数位被复制到寄存器条目的相应字段，并且测试指数位以确定组件操作数是否被归一化。 当组件操作数被归一化时，设置与组件操作数相对应的隐式位。
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