Network switch which supports TDM, ATM, and variable length packet traffic and includes automatic fault/congestion correction
    12.
    发明授权
    Network switch which supports TDM, ATM, and variable length packet traffic and includes automatic fault/congestion correction 有权
    支持TDM,ATM和可变长度数据包流量的网络交换机,包括自动故障/拥塞纠正

    公开(公告)号:US06646983B1

    公开(公告)日:2003-11-11

    申请号:US09717998

    申请日:2000-11-21

    CPC classification number: H04L12/6402 H04L2012/6413

    Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

    Abstract translation: 网络交换机包括至少一个端口处理器和至少一个开关元件。 端口处理器具有SONET OC-x接口(用于TDM流量),UTOPIA接口(用于ATM和数据包流量)以及与交换机元件的接口。 在一个实施例中,端口处理器具有等同于OC-48的总I / O带宽,并且交换单元具有12×12端口,总带宽为30Gbps。 典型的交换机包括多个端口处理器和交换机元件。 使用9行×1700个时隙的数据帧将ATM,TDM和分组数据从端口处理器通过一个或多个交换元件传输到相同或另一个端口处理器。 每帧在125微秒内传输; 每行在13.89微秒。 每个插槽包括一个4位标签加上一个4字节的有效载荷。 时隙带宽为2.592Mbps,足够大以承载具有开销的E-1信号。 4位标签是交叉连接指针,当指定TDM连接时,该指针将被设置。 帧的最后20个时隙被保留用于链路开销。 因此,该帧能够承载1,680个E-1 TDM信号的等效物。 对于ATM和分组数据,为64字节的有效载荷定义了16个时隙的PDU(协议数据单元)。 PDU通过具有28位路由标签的交换机进行自路由,该路由标签允许通过每个阶段使用4位的七个交换阶段进行路由。 在保持TDM定时的同时,在ATM和分组连接之间仲裁带宽。

    Method and apparatus for switching ATM, TDM, and packet data through a single communications switch while maintaining TDM timing
    13.
    发明授权
    Method and apparatus for switching ATM, TDM, and packet data through a single communications switch while maintaining TDM timing 有权
    用于在保持TDM定时的同时通过单个通信交换机切换ATM,TDM和分组数据的方法和装置

    公开(公告)号:US06631130B1

    公开(公告)日:2003-10-07

    申请号:US09717440

    申请日:2000-11-21

    Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

    Abstract translation: 网络交换机包括至少一个端口处理器和至少一个开关元件。 端口处理器具有SONET OC-x接口(用于TDM流量),UTOPIA接口(用于ATM和数据包流量)以及与交换机元件的接口。 在一个实施例中,端口处理器具有等同于OC-48的总I / O带宽,并且交换单元具有12×12端口,总带宽为30Gbps。 典型的交换机包括多个端口处理器和交换机元件。 使用9行×1700个时隙的数据帧将ATM,TDM和分组数据从端口处理器通过一个或多个交换元件传输到相同或另一个端口处理器。 每帧在125微秒内传输; 每行在13.89微秒。 每个插槽包括一个4位标签加上一个4字节的有效载荷。 时隙带宽为2.592Mbps,足够大以承载具有开销的E-1信号。 4位标签是交叉连接指针,当指定TDM连接时,该指针将被设置。 帧的最后20个时隙被保留用于链路开销。 因此,该帧能够承载1,680个E-1 TDM信号的等效物。 对于ATM和分组数据,为64字节的有效载荷定义了16个时隙的PDU(协议数据单元)。 PDU通过具有28位路由标签的交换机进行自路由,该路由标签允许通过每个阶段使用4位的七个交换阶段进行路由。 在保持TDM定时的同时,在ATM和分组连接之间仲裁带宽。

    Method and apparatus for managing multiple ATM cell queues
    14.
    发明授权
    Method and apparatus for managing multiple ATM cell queues 有权
    用于管理多个ATM信元队列的方法和装置

    公开(公告)号:US06246682B1

    公开(公告)日:2001-06-12

    申请号:US09263289

    申请日:1999-03-05

    CPC classification number: H04L12/5601 H04L49/108 H04L49/203 H04L2012/5681

    Abstract: Methods for managing multiple queues of ATM cells in shared RAM while efficiently supporting multicasting include providing a common memory for storing ATM cells and for storing at least one pointer to each ATM cell stored, providing a management memory for storing an index to the pointers stored in common memory, a table for each multicast session, and an index to the free space in common memory. According to the presently preferred method, cells entering the switch are examined, placed in shared RAM, and a pointer to the RAM location is written in another location in the shared RAM. Table entries in management RAM are updated each time a cell is added to a queue. When a multicast session is begun, a multicast table is created with all of the addresses in the multicast session. When a multicast cell is received, the multicast session table is consulted and pointers to the cell are copied to queues for each address in the table. When a pointer exits a queue, the cell pointed to by the pointer is read and transmitted to the address of the queue. As the cell is read, the destination count for the cell is decremented. When the destination count is reduced to zero, the RAM location used to store the cell is added to the free list. Each time a pointer is read, the table entry for the affected queue is updated. When the queue becomes empty, an active bit in the table entry is toggled.

    Abstract translation: 在有效地支持多播的同时管理共享RAM中的ATM信元的多个队列的方法包括:提供用于存储ATM信元的公共存储器和用于存储至少一个指向存储的每个ATM信元的指针,提供管理存储器,用于存储指向存储的指针的索引 公共存储器,每个多播会话的表,以及公共存储器中的可用空间的索引。 根据目前优选的方法,检查进入开关的单元,放置在共享RAM中,并将指向RAM位置的指针写入共享RAM中的另一位置。 每当将单元格添加到队列时,管理RAM中的表条目将被更新。 当多播会话开始时,将创建组播表,其中包含组播会话中的所有地址。 当接收到多播小区时,查询组播会话表,并将指向小区的指针复制到表中每个地址的队列中。 当指针退出队列时,指针指向的单元被读取并发送到队列的地址。 当单元被读取时,单元的目的地计数递减。 当目的地计数减少到零时,用于存储单元的RAM位置被添加到空闲列表中。 每次读取指针时,将更新受影响队列的表条目。 当队列变空时,表条目中的活动位被切换。

    Methods and apparatus for managing traffic in an atm network
    15.
    发明授权
    Methods and apparatus for managing traffic in an atm network 失效
    用于管理大气网络中的流量的方法和装置

    公开(公告)号:US06243359B1

    公开(公告)日:2001-06-05

    申请号:US09302200

    申请日:1999-04-29

    Abstract: The apparatus includes a separate line side inlet queue for each GFR VC, a single network side outlet queue for all GFR VCs, a single network side inlet queue for all GFR VCs, a single line side outlet bulk processing queue with a post queue packet processor followed by separate line side outlet queues for each line, a network side outlet queue monitor, and a line side inlet queue controller. The network side outlet queue monitor is coupled to the line side inlet queue controller so that the network side outlet queue monitor can send messages to the line side inlet queue controller. According to one of the methods of the invention, the network side outlet queue monitor sends messages to the line side inlet queue controller directing the line side inlet queue controller to send data from the line side GFR queues based on the status of the network side outlet GFR queue. According to another method of the invention, the line to side inlet queue controller discards packets for a GFR VC if congestion is indicated. According to still another method of the invention, the post queue packet processor discards packets above the PCR if the size of the line side outlet bulk processing queue exceeds a threshold size and discards packets above the MCR if discarding packets above the PCR fails to sufficiently reduce the size of the line side outlet bulk processing queue.

    Abstract translation: 该设备包括用于每个GFR VC的单独的线路侧入口队列,用于所有GFR VC的单个网络侧出口队列,用于所有GFR VC的单个网络侧入口队列,具有后队列分组处理器的单个线路侧出口批量处理队列 后面是每一行的单独的线路侧出口队列,网络侧出口队列监视器和线路侧入口队列控制器。 网络侧出口队列监视器耦合到线路侧入口队列控制器,使网络侧出口队列监视器可以向线路侧入口队列控制器发送消息。 根据本发明的一种方法,网络侧出口队列监视器向线路侧入口队列控制器发送消息,指示线路侧入口队列控制器基于网络侧出口的状态从线路侧GFR队列发送数据 GFR队列 根据本发明的另一种方法,如果指示拥塞,则线对侧入口队列控制器丢弃用于GFR VC的分组。 根据本发明的另一种方法,如果线路侧出口批量处理队列的大小超过阈值大小并且如果丢弃上述PCR上的分组,则丢弃MCR上方的分组,则后队列分组处理器丢弃PCR上方的分组, 线路端口批量处理队列的大小。

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