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11.发明授权
公开(公告)号：US6061706A
公开(公告)日：2000-05-09
申请号：US949036
申请日：1997-10-10
申请人： Weixin Gai , Hongyi Chen
发明人： Weixin Gai , Hongyi Chen
CPC分类号： G06F7/728 , G06F2207/3884
摘要： A systolic linear-array modular multiplier is provided, which can perform the modular multiplication algorithm of P. L. Montgomery more efficiently. The total execution time for n-bit modular multiplication is 2n+11 cycles. The modular multiplier includes a linear array of processing elements which is constructed based on a pipeline architecture that can reduce the computation procedure by one clock period. Each of the processing elements is simple in structure, which is composed of four full adders and fourteen flip-flops. For n-bit modular multiplication, a total number of 46n+184 gates is required, which is substantially less as compared to the prior art, so that manufacturing cost of the modular multiplier can be significantly reduced. These features make the modular multiplier suitable for use in VLSI implementation of modular exponentiation which is the kernel computation in many public-key cryptosystems, such as the RSA (Rivest-Shamir-Adleman) system. With the 0.8 .mu.m CMOS technology, a clock signal up to 180 MHz can be used. In average, for n-bit modular multiplication, the encryption speed can reach 116 Kbit/s (kilobits per second), which is substantially twice that achieved by the prior art.
摘要翻译： 提供了一种收缩线性阵列模乘法，可以更有效地执行P.L. Montgomery的模乘法。 n位模乘的总执行时间为2n + 11个周期。 模数乘法器包括一个基于流水线结构构造的处理元件的线性阵列，可以将计算过程减少一个时钟周期。 每个处理元件的结构简单，由四个全加器和十四个触发器组成。 对于n位模乘法，需要总共46n + 184个门，这与现有技术相比要小得多，因此可以大大减少模乘器的制造成本。 这些特征使得模块乘法器适用于VLSI实现模幂运算，这是多指令密码系统中的核心计算，如RSA（Rivest-Shamir-Adleman）系统。 采用0.8微米CMOS技术，可以使用高达180 MHz的时钟信号。 平均来说，对于n位模乘，加密速度可以达到116Kbit / s（千比特每秒），这是现有技术实现的两倍。
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公开(公告)号：US07512178B2
公开(公告)日：2009-03-31
申请号：US11618189
申请日：2006-12-29
申请人： Yoichi Koyanagi , Yasuo Hidaka , Weixin Gai , Hirotaka Tamura
发明人： Yoichi Koyanagi , Yasuo Hidaka , Weixin Gai , Hirotaka Tamura
CPC分类号： H04L25/03343
摘要： Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.
摘要翻译： 信号均衡包括接收具有振幅的数据序列信号。 确定可操作以均衡数据序列信号的数据序列信号的调整。 产生用于根据调整来调节数据序列信号的幅度的控制信号，其中控制信号具有模拟形式。 使用控制信号调整数据序列信号的幅度，以便均衡数据序列信号。
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公开(公告)号：US20070110147A1
公开(公告)日：2007-05-17
申请号：US11618189
申请日：2006-12-29
申请人： Yoichi Koyanagi , Yasuo Hidaka , Weixin Gai , Hirotaka Tamura
发明人： Yoichi Koyanagi , Yasuo Hidaka , Weixin Gai , Hirotaka Tamura
CPC分类号： H04L25/03343
摘要： Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.
摘要翻译： 信号均衡包括接收具有振幅的数据序列信号。 确定可操作以均衡数据序列信号的数据序列信号的调整。 产生用于根据调整来调节数据序列信号的幅度的控制信号，其中控制信号具有模拟形式。 使用控制信号调整数据序列信号的幅度，以便均衡数据序列信号。
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公开(公告)号：US06246294B1
公开(公告)日：2001-06-12
申请号：US09249490
申请日：1999-02-12
申请人： Weixin Gai
发明人： Weixin Gai
IPC分类号： H03L100
CPC分类号： H03L7/0995 , H03L7/0895 , H03L7/18
摘要： A phase-locked loop system that generates an output signal having low jitter includes a phase frequency detector, a charge pump, a low jitter voltage-controlled oscillator, a system low-pass filter, and a divider. The phase frequency detector couples to an input signal line. The charge pump couples to the phase frequency detector, the low jitter voltage controlled oscillator, and the low pass filter. The low-jitter voltage controlled oscillator couples to an output signal line and to the divider. The divider couples to the phase frequency detector through a feedback signal line. The low jitter voltage controlled oscillator includes a voltage regulator, a low-pass filter, and a ring oscillator. The low jitter voltage controlled oscillator may also include a current driver. The voltage regulator couples to the low-pass filter and to the input signal line. The low-pass filter couples to the optional current driver and the ring oscillator. The ring oscillator couples to the charge pump, the optional low pass filter, the output signal line, and the divider. A method also discloses generating a low jitter output signal using a supply noise immunity low jitter voltage controlled oscillator.
摘要翻译： 产生具有低抖动的输出信号的锁相环系统包括相位频率检测器，电荷泵，低抖动电压控制振荡器，系统低通滤波器和分频器。 相位频率检测器耦合到输入信号线。 电荷泵耦合到相位频率检测器，低抖动压控振荡器和低通滤波器。 低抖动压控振荡器耦合到输出信号线和分频器。 分频器通过反馈信号线耦合到相位频率检测器。 低抖动电压控制振荡器包括电压调节器，低通滤波器和环形振荡器。 低抖动压控振荡器还可以包括电流驱动器。 电压调节器耦合到低通滤波器和输入信号线。 低通滤波器耦合到可选电流驱动器和环形振荡器。 环形振荡器耦合到电荷泵，可选的低通滤波器，输出信号线和分频器。 一种方法还公开了使用电源抗噪声低抖动压控振荡器产生低抖动输出信号。
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公开(公告)号：US5966040A
公开(公告)日：1999-10-12
申请号：US938747
申请日：1997-09-26
申请人： Weixin Gai , Hongyi Chen
发明人： Weixin Gai , Hongyi Chen
CPC分类号： G06G7/164
摘要： A current-mode four-quadrant analog multiplier is provided, which is constructed based on CMOS (complementary metal-oxide semiconductor) technology, capable of generating an output current signal which is proportional in magnitude to the product of two input current signals. This current-mode analog multiplier is designed based on the translinear circuit principle. The current-mode analog multiplier has high precision, wide current dynamic range, and is insensitive to temperature and process, suitable for use in VLSI implementation of many analog circuits and systems, such as fuzzy logic controllers and analog neural networks.
摘要翻译： 提供了基于CMOS（互补金属氧化物半导体）技术构建的电流模式四象限模拟乘法器，其能够产生与两个输入电流信号的乘积成比例的输出电流信号。 该电流模式模拟乘法器是基于跨线电路原理设计的。 电流模式模拟乘法器具有高精度，宽电流动态范围，对温度和过程不敏感，适用于许多模拟电路和系统（如模糊逻辑控制器和模拟神经网络）的VLSI实现。
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