公开(公告)号：US20090316769A1

公开(公告)日：2009-12-24

申请号：US12488777

申请日：2009-06-22

申请人： Yasuo Hidaka ,  Weixin Gai

发明人： Yasuo Hidaka ,  Weixin Gai

IPC分类号： H03D1/04 ,  H03H7/30

CPC分类号： H04L25/03057

摘要： In one embodiment, a method includes receiving an input signal from a receiver, receiving a data clock (DCLK) signal, and receiving a boundary clock (BCLK) signal. The method includes, based on the input signal and the DCLK signal, recovering data from the input signal to produce a first output signal. The method includes, based on the input signal and the BCLK signal, recovering boundaries between bits in the input signal to produce a second output signal. The method includes, based on the first and second output signals, producing the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs.

摘要翻译： 在一个实施例中，一种方法包括从接收器接收输入信号，接收数据时钟（DCLK）信号和接收边界时钟（BCLK）信号。 该方法基于输入信号和DCLK信号，从输入信号中恢复数据以产生第一输出信号。 该方法基于输入信号和BCLK信号，恢复输入信号中的比特之间的边界以产生第二输出信号。 该方法包括基于第一和第二输出信号产生DCLK和BCLK信号，其中DCLK信号相对于小于约0.5单位间隔（UI）的BCLK信号被延迟并且大于或等于大约零UI 。

公开(公告)号：US20050184801A1

公开(公告)日：2005-08-25

申请号：US10783070

申请日：2004-02-20

申请人： Weixin Gai ,  Yasuo Hidaka

发明人： Weixin Gai ,  Yasuo Hidaka

IPC分类号： H03F3/34 ,  H03F1/34 ,  H03F3/21 ,  H03F3/45 ,  H03G5/16 ,  H04B3/14 ,  H04L25/03 ,  H03F1/02

CPC分类号： H03F3/211 ,  H03F3/45179 ,  H03F3/45475 ,  H03F3/45659 ,  H03F3/45744 ,  H03F3/45968 ,  H03F2200/78 ,  H03F2203/45652 ,  H03F2203/45702 ,  H03G5/165 ,  H04L2025/03445

摘要： A method for correcting DC offsets in a multi-stage amplifier includes determining a DC offset imparted by a multi-stage amplifier to an input signal. The method further includes applying a correction voltage to a plurality of selected stages in the multi-stage amplifier. The total correction voltage applied substantially negates the DC offset imparted by the multi-stage amplifier.

摘要翻译： 用于校正多级放大器中的DC偏移的方法包括：确定由多级放大器给予输入信号的DC偏移。 该方法还包括向多级放大器中的多个选定级施加校正电压。 所施加的总校正电压基本上否定由多级放大器赋予的DC偏移。

公开(公告)号：US07295605B2

公开(公告)日：2007-11-13

申请号：US10783170

申请日：2004-02-20

申请人： Weixin Gai ,  Yasuo Hidaka

发明人： Weixin Gai ,  Yasuo Hidaka

IPC分类号： H03K5/159

CPC分类号： H04L25/03038 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45748 ,  H03F3/45973 ,  H03F2203/45424 ,  H03F2203/45458 ,  H03F2203/45652 ,  H03F2203/45702 ,  H03G5/165 ,  H04L25/061 ,  H04L2025/03445 ,  H04L2025/03592

摘要： A method for compensating for attenuation in an input signal includes receiving an input signal, communicating a first portion of the input signal on a first path, communicating a second portion of the input signal on a second path, and communicating a third portion of the input signal on a third path. The method also includes applying a first gain to the first portion of the input signal, applying a first-order mathematical operation and a second gain to the second portion of the input signal, and applying a second-order mathematical operation and a third gain to the portion of the input signal. The method further includes recombining the first portion, the second portion, and the third portion into an output signal.

摘要翻译： 用于补偿输入信号中的衰减的方法包括接收输入信号，在第一路径上传送输入信号的第一部分，在第二路径上传送输入信号的第二部分，以及传送输入的第三部分 信号在第三条路径上。 该方法还包括对输入信号的第一部分施加第一增益，向输入信号的第二部分应用一阶数学运算和第二增益，以及将二阶数学运算和第三增益应用于 输入信号的一部分。 该方法还包括将第一部分，第二部分和第三部分重新组合成输出信号。

公开(公告)号：US07034608B2

公开(公告)日：2006-04-25

申请号：US10783070

申请日：2004-02-20

申请人： Weixin Gai ,  Yasuo Hidaka

发明人： Weixin Gai ,  Yasuo Hidaka

IPC分类号： H03F3/45

CPC分类号： H03F3/211 ,  H03F3/45179 ,  H03F3/45475 ,  H03F3/45659 ,  H03F3/45744 ,  H03F3/45968 ,  H03F2200/78 ,  H03F2203/45652 ,  H03F2203/45702 ,  H03G5/165 ,  H04L2025/03445

摘要： A method for correcting DC offsets in a multi-stage amplifier includes determining a DC offset imparted by a multi-stage amplifier to an input signal. The method further includes applying a correction voltage to a plurality of selected stages in the multi-stage amplifier. The total correction voltage applied substantially negates the DC offset imparted by the multi-stage amplifier.

摘要翻译： 用于校正多级放大器中的DC偏移的方法包括：确定由多级放大器给予输入信号的DC偏移。 该方法还包括向多级放大器中的多个选定级施加校正电压。 所施加的总校正电压基本上否定由多级放大器赋予的DC偏移。

公开(公告)号：US06418500B1

公开(公告)日：2002-07-09

申请号：US09249009

申请日：1999-02-12

申请人： Weixin Gai ,  Hirotaka Tamura

发明人： Weixin Gai ,  Hirotaka Tamura

IPC分类号： G06F1340

CPC分类号： H04L25/0278 ,  G06F13/4086 ,  H04L25/0272

摘要： A termination system includes a termination element, a reference resistance system, and a feedback control system. The termination element includes one or more transfer gates. The transfer gates are comprised of one or more transistors that provide some resistance value that is dependent upon which transistors are in an on state or an off state. The termination element is connected to a driver system and an electrical signal line. The reference resistance system is used to provide a reference resistance value that is substantially equivalent to a line characteristic impedance of the electrical signal line. The feedback control system is connected to the reference resistance system and the termination element. The feedback control system uses the reference resistance system to generate an adjustment signal for the termination element so that the resistance value of the termination element substantially matches the line characteristic impedance of the electrical signal line. The adjustment signal places the transistors of the transfer gate in an on state or an off state so that the resistance value of the termination element is accordingly matched to the line characteristic impedance. In addition, a method for adjusting a resistance value of a terminator element is described. A method for generating an adjustment signal is also described.

摘要翻译： 终端系统包括终端元件，参考电阻系统和反馈控制系统。 终端元件包括一个或多个传输门。 传输门由提供一些电阻值的一个或多个晶体管组成，这些电阻值取决于哪个晶体管处于导通状态或断开状态。 终端元件连接到驱动器系统和电信号线。 参考电阻系统用于提供基本上等于电信号线的线特性阻抗的参考电阻值。 反馈控制系统连接到参考电阻系统和终端元件。 反馈控制系统使用参考电阻系统来产生用于终端元件的调整信号，使得终端元件的电阻值基本上与电信号线的线特性阻抗匹配。 调整信号使传输栅极的晶体管处于导通状态或截止状态，使得端接元件的电阻值相应地与线特性阻抗匹配。 此外，描述了用于调节终端元件的电阻值的方法。 还描述了一种用于产生调整信号的方法。

公开(公告)号：US08270464B2

公开(公告)日：2012-09-18

申请号：US12488777

申请日：2009-06-22

申请人： Yasuo Hidaka ,  Weixin Gai

发明人： Yasuo Hidaka ,  Weixin Gai

IPC分类号： H03H7/30

CPC分类号： H04L25/03057

摘要： In one embodiment, a method includes receiving an input signal from a receiver, receiving a data clock (DCLK) signal, and receiving a boundary clock (BCLK) signal. The method includes, based on the input signal and the DCLK signal, recovering data from the input signal to produce a first output signal. The method includes, based on the input signal and the BCLK signal, recovering boundaries between bits in the input signal to produce a second output signal. The method includes, based on the first and second output signals, producing the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs.

摘要翻译： 在一个实施例中，一种方法包括从接收器接收输入信号，接收数据时钟（DCLK）信号和接收边界时钟（BCLK）信号。 该方法基于输入信号和DCLK信号，从输入信号中恢复数据以产生第一输出信号。 该方法基于输入信号和BCLK信号，恢复输入信号中的比特之间的边界以产生第二输出信号。 该方法包括基于第一和第二输出信号产生DCLK和BCLK信号，其中DCLK信号相对于小于约0.5单位间隔（UI）的BCLK信号被延迟并且大于或等于大约零UI 。

公开(公告)号：US07778344B2

公开(公告)日：2010-08-17

申请号：US11420391

申请日：2006-05-25

申请人： Weixin Gai

发明人： Weixin Gai

IPC分类号： H04L27/10

CPC分类号： H03K5/15 ,  H03K2005/00286

摘要： A system for combining a plurality of signals of various phases having a wide frequency range includes a signal transmuter configured to receive a plurality of input signals of different phases. The signal transmuter is also configured to generate at least one output signal based on one or more of the input signals. The system also includes at least one switch configured to receive a control signal and operable to selectively couple at least one associated capacitor to the at least one output signal. The coupling is such that the capacitor is coupled to the at least one output signal when the switch is closed. The control signal is set to substantially reduce the saturation of the at least one output signal.

摘要翻译： 用于组合具有宽频率范围的各种相位的多个信号的系统包括被配置为接收不同相位的多个输入信号的信号变换器。 信号传输器还被配置为基于输入信号中的一个或多个产生至少一个输出信号。 该系统还包括至少一个开关，其被配置为接收控制信号并且可操作以选择性地将至少一个相关联的电容器耦合到至少一个输出信号。 耦合使得当开关闭合时，电容器耦合到至少一个输出信号。 控制信号被设置为基本上降低至少一个输出信号的饱和度。

公开(公告)号：US20070274413A1

公开(公告)日：2007-11-29

申请号：US11420391

申请日：2006-05-25

申请人： Weixin Gai

发明人： Weixin Gai

IPC分类号： H04L27/10

CPC分类号： H03K5/15 ,  H03K2005/00286

摘要： A system for combining a plurality of signals of various phases having a wide frequency range includes a signal transmuter configured to receive a plurality of input signals of different phases. The signal transmuter is also configured to generate at least one output signal based on one or more of the input signals. The system also includes at least one switch configured to receive a control signal and operable to selectively couple at least one associated capacitor to the at least one output signal. The coupling is such that the capacitor is coupled to the at least one output signal when the switch is closed. The control signal is set to substantially reduce the saturation of the at least one output signal.

摘要翻译： 用于组合具有宽频率范围的各种相位的多个信号的系统包括被配置为接收不同相位的多个输入信号的信号变换器。 信号传输器还被配置为基于输入信号中的一个或多个产生至少一个输出信号。 该系统还包括至少一个开关，其被配置为接收控制信号并且可操作以选择性地将至少一个相关联的电容器耦合到至少一个输出信号。 耦合使得当开关闭合时，电容器耦合到至少一个输出信号。 控制信号被设置为基本上降低至少一个输出信号的饱和度。

公开(公告)号：US07173965B2

公开(公告)日：2007-02-06

申请号：US10357691

申请日：2003-02-03

申请人： Yoichi Koyanagi ,  Yasuo Hidaka ,  Weixin Gai ,  Hirotaka Tamura

发明人： Yoichi Koyanagi ,  Yasuo Hidaka ,  Weixin Gai ,  Hirotaka Tamura

IPC分类号： H03K5/159 ,  H04B3/04 ,  H04B3/14 ,  H01P9/00

CPC分类号： H04L25/03343

摘要： Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.

摘要翻译： 信号均衡包括接收具有振幅的数据序列信号。 确定可操作以均衡数据序列信号的数据序列信号的调整。 产生用于根据调整来调节数据序列信号的幅度的控制信号，其中控制信号具有模拟形式。 使用控制信号调整数据序列信号的幅度，以便均衡数据序列信号。

公开(公告)号：US20050185710A1

公开(公告)日：2005-08-25

申请号：US10783170

申请日：2004-02-20

申请人： Weixin Gai ,  Yasuo Hidaka

发明人： Weixin Gai ,  Yasuo Hidaka

IPC分类号： H04B3/04 ,  H03F1/02 ,  H03F3/45 ,  H03G5/16 ,  H04L25/03 ,  H04L25/06

CPC分类号： H04L25/03038 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45748 ,  H03F3/45973 ,  H03F2203/45424 ,  H03F2203/45458 ,  H03F2203/45652 ,  H03F2203/45702 ,  H03G5/165 ,  H04L25/061 ,  H04L2025/03445 ,  H04L2025/03592

摘要： A method for compensating for attenuation in an input signal includes receiving an input signal, communicating a first portion of the input signal on a first path, communicating a second portion of the input signal on a second path, and communicating a third portion of the input signal on a third path. The method also includes applying a first gain to the first portion of the input signal, applying a first-order mathematical operation and a second gain to the second portion of the input signal, and applying a second-order mathematical operation and a third gain to the portion of the input signal. The method further includes recombining the first portion, the second portion, and the third portion into an output signal.

摘要翻译： 用于补偿输入信号中的衰减的方法包括接收输入信号，在第一路径上传送输入信号的第一部分，在第二路径上传送输入信号的第二部分，以及传送输入的第三部分 信号在第三条路径上。 该方法还包括对输入信号的第一部分施加第一增益，向输入信号的第二部分应用一阶数学运算和第二增益，以及将二阶数学运算和第三增益应用于 输入信号的一部分。 该方法还包括将第一部分，第二部分和第三部分重新组合成输出信号。