公开(公告)号：US12175073B2

公开(公告)日：2024-12-24

申请号：US17139496

申请日：2020-12-31

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Varun Agrawal ,  Niti Madan

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods for reusing remote registers in processing in memory (PIM) are disclosed. A system includes at least a host processor, a memory controller, and a PIM device. When the memory controller receives, from the host processor, an operation targeting the PIM device, the memory controller determines whether an optimization can be applied to the operation. The memory controller converts the operation into N PIM commands if the optimization is not applicable. Otherwise, the memory controller converts the operation into a N−1 PIM commands if the optimization is applicable. For example, if the operation involves reusing a constant value, a copy command can be omitted, resulting in memory bandwidth reduction and power consumption savings. In one scenario, the memory controller includes a constant-value cache, and the memory controller performs a lookup of the constant-value cache to determine if the optimization is applicable for a given operation.

公开(公告)号：US12066950B2

公开(公告)日：2024-08-20

申请号：US17561454

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Niti Madan ,  John Kalamatianos

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F12/0207 ,  G06F12/0882

Abstract: An approach is provided for managing PIM commands and non-PIM commands at a memory controller. A memory controller enqueues PIM commands and non-PIM commands and selects the next command to process based upon various selection criteria. The memory controller maintains and uses a page table to properly configure memory elements, such as banks in a memory module, for the next memory command, whether a PIM command or a non-PIM command. The page table tracks the status of memory elements as of the most recent memory command that was issued. The page table includes an “All Bank” entry that indicates the status of banks after processing the most recent PIM command. For example, the All Banks entry indicates whether all the banks have a row open and if so, specifies the open row for all the banks.

公开(公告)号：US12026401B2

公开(公告)日：2024-07-02

申请号：US17855109

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Niti Madan ,  Yasuko Eckert ,  Varun Agrawal ,  John Kalamatianos

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second command is issued to open the additional row after the row is last accessed by the instruction.

公开(公告)号：US20240103745A1

公开(公告)日：2024-03-28

申请号：US17954784

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Niti Madan ,  Johnathan Robert Alsop ,  Alexandru Dutu ,  Mahzabeen Islam ,  Yasuko Eckert ,  Nuwan S Jayasena

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory controller coupled to a memory module receives both processing-in-memory (PIM) requests and memory requests from a host (e.g., a host processor). The memory controller issues PIM requests to one group of memory banks and concurrently issues memory requests to one or more other groups of memory banks. Accordingly, memory requests are performed on groups of memory banks that would otherwise be idle while PIM requests are performed on the one group of memory banks. Optionally, the memory controller coupled to the memory module also takes various actions when switching between operating in a PIM mode and a non-processing-in-memory mode to reduce or hide overhead when switching between the two modes.