公开(公告)号：US12169758B2

公开(公告)日：2024-12-17

申请号：US17491304

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Salonik Resch ,  Anthony Gutierrez ,  Yasuko Eckert ,  Vedula Venkata Srikant Bharadwaj ,  Mark H. Oskin

IPC: G06F9/48 ,  G06F11/36 ,  G06N10/00

Abstract: An electronic device includes a quantum processor having a plurality of qubits and a processor. The processor runs a plurality of instances of a quantum program substantially in parallel on the quantum processor using a separate set of qubits from among the plurality of qubits for each instance of the quantum program. The processor then acquires an output for each instance of the quantum program from the quantum processor. The processor next uses the outputs for generating an output of the quantum program.

公开(公告)号：US11797455B2

公开(公告)日：2023-10-24

申请号：US16600897

申请日：2019-10-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jieming Yin ,  Subhash Sethumurugan ,  Yasuko Eckert

IPC: G06F12/12 ,  G06F12/0891 ,  G06F12/0855 ,  G06F12/126 ,  G06F12/0897 ,  G06F12/0871

CPC classification number: G06F12/0891 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0897 ,  G06F12/126

Abstract: A cache of a processor includes a cache controller to implement a cache management policy for the insertion and replacement of cache lines of the cache. The cache management policy assigns replacement priority levels to each cache line of at least a subset of cache lines in a region of the cache based on a comparison of a number of accesses to a cache set having a way that stores a cache line since the cache line was last accessed to a reuse distance determined for the region of the cache, wherein the reuse distance represents an average number of accesses to a given cache set of the region between accesses to any given cache line of the cache set.

公开(公告)号：US11704277B2

公开(公告)日：2023-07-18

申请号：US16716390

申请日：2019-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Majed Valad Beigi ,  Yasuko Eckert ,  Dongping Zhang

IPC: G06F15/82 ,  G06N10/00 ,  G06N10/60 ,  G06N10/70

CPC classification number: G06F15/82 ,  G06N10/00 ,  G06N10/60 ,  G06N10/70

Abstract: Systems and methods for efficiently routing qubits in a quantum computing system include selecting bubble nodes and routing qubits to the bubble nodes. The systems and methods further include dividing a system of nodes into regions and selecting a bubble node for each region. The systems and methods further include using super bubble nodes with reliable links connected to other super bubble nodes and bubble nodes to improve cross-region operations.

公开(公告)号：US20230094508A1

公开(公告)日：2023-03-30

申请号：US17491304

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Salonik Resch ,  Anthony Gutierrez ,  Yasuko Eckert ,  Vedula Venkata Srikant Bharadwaj ,  Mark H. Oskin

IPC: G06N10/00 ,  G06F11/36 ,  G06F9/48

Abstract: An electronic device includes a quantum processor having a plurality of qubits and a processor. The processor runs a plurality of instances of a quantum program substantially in parallel on the quantum processor using a separate set of qubits from among the plurality of qubits for each instance of the quantum program. The processor then acquires an output for each instance of the quantum program from the quantum processor. The processor next uses the outputs for generating an output of the quantum program.

公开(公告)号：US20210232501A1

公开(公告)日：2021-07-29

申请号：US16776416

申请日：2020-01-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Weon Taek Na ,  Yasuko Eckert ,  Mark H. Oskin ,  Gabriel H. Loh ,  William Louie Walker ,  Michael Warren Boyer

IPC: G06F12/0815 ,  G06F16/22

Abstract: An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will “hit” the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.

公开(公告)号：US20210182234A1

公开(公告)日：2021-06-17

申请号：US16716390

申请日：2019-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Majed Valad Beigi ,  Yasuko Eckert ,  Dongping Zhang

IPC: G06F15/82 ,  G06N10/00

Abstract: Systems and methods for efficiently routing qubits in a quantum computing system include selecting bubble nodes and routing qubits to the bubble nodes. The systems and methods further include dividing a system of nodes into regions and selecting a bubble node for each region. The systems and methods further include using super bubble nodes with reliable links connected to other super bubble nodes and bubble nodes to improve cross-region operations.

公开(公告)号：US20200167328A1

公开(公告)日：2020-05-28

申请号：US16202082

申请日：2018-11-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Mohamed Assem Ibrahim ,  Onur Kayiran ,  Yasuko Eckert

IPC: G06F16/22 ,  G06F16/901

Abstract: A portion of a graph dataset is generated for each computing node in a distributed computing system by, for each subject vertex in a graph, recording for the computing node an offset for the subject vertex, where the offset references a first position in an edge array for the computing node, and for each edge of a set of edges coupled with the subject vertex in the graph, calculating an edge value for the edge based on a connected vertex identifier identifying a vertex coupled with the subject vertex via the edge. When the edge value is assigned to the first position, the edge value is determined by a first calculation, and when the edge value is assigned to position subsequent to the first position, the edge value is determined by a second calculation. In the computing node, the edge value is recorded in the edge array.

公开(公告)号：US10310981B2

公开(公告)日：2019-06-04

申请号：US15268953

申请日：2016-09-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Nuwan Jayasena ,  Reena Panda ,  Onur Kayiran ,  Michael W. Boyer

IPC: G06F12/00 ,  G06F12/0862 ,  G06F13/00 ,  G06F13/28

Abstract: A method and apparatus for performing memory prefetching includes determining whether to initiate prefetching. Upon a determination to initiate prefetching, a first memory row is determined as a suitable prefetch candidate, and it is determined whether a particular set of one or more cachelines of the first memory row is to be prefetched.

公开(公告)号：US20180365167A1

公开(公告)日：2018-12-20

申请号：US15626623

申请日：2017-06-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Thiruvengadam Vijayaraghavan ,  Gabriel H. Loh

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/68

Abstract: A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.

公开(公告)号：US20180157589A1

公开(公告)日：2018-06-07

申请号：US15370734

申请日：2016-12-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Yasuko Eckert

IPC: G06F12/0815 ,  G06F12/084

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/0824 ,  G06F12/084 ,  G06F2212/1024 ,  G06F2212/507 ,  G06F2212/60 ,  G06F2212/621

Abstract: A distributed shared-memory system includes several nodes that each have one or more processor cores, caches, local main memory, and a directory. Each node further includes predictors that use historical memory access information to predict future coherence permission requirements and speculatively initiate coherence operations. In one embodiment, predictors are included at processor cores for monitoring a memory access stream (e.g., historical sequence of memory addresses referenced by a processor core) and predicting addresses of future accesses. In another embodiment, predictors are included at the directory of each node for monitoring memory access traffic and coherence-related activities for individual cache lines to predict future demands for particular cache lines. In other embodiments, predictors are included at both the processor cores and directory of each node. Predictions from the predictors are used to initiate coherence operations to speculatively request promotion or demotion of coherence permissions.