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    Accelerating relaxed remote atomics on multiple writer operations
    2.
    发明授权
    Accelerating relaxed remote atomics on multiple writer operations 有权

    公开(公告)号：US12105957B2

    公开(公告)日：2024-10-01

    申请号：US18087964

    申请日：2022-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Kalamatianos ,  Karthik Ramu Sangaiah ,  Anthony Thomas Gutierrez

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.

    Accessing a Cache Based on an Address Translation Buffer Result
    5.
    发明公开
    Accessing a Cache Based on an Address Translation Buffer Result 审中-公开

    公开(公告)号：US20240193097A1

    公开(公告)日：2024-06-13

    申请号：US18064155

    申请日：2022-12-09

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jagadish B. Kotra ,  John Kalamatianos

    IPC: G06F12/1045 ,  G06F12/0897

    CPC classification number: G06F12/1045 ,  G06F12/0897

    Abstract: Address translation is performed to translate a virtual address targeted by a memory request (e.g., a load or memory request for data or an instruction) to a physical address. This translation is performed using an address translation buffer, e.g., a translation lookaside buffer (TLB). One or more actions are taken to reduce data access latencies for memory requests in the event of a TLB miss where the virtual address to physical address translation is not in the TLB. Examples of actions that are performed in various implementations in response to a TLB miss include bypassing level 1 (L1) and level 2 (L2) caches in the memory system, and speculatively sending the memory request to the L2 cache while checking whether the memory request is satisfied by the L1 cache.

    Method and apparatus for virtualizing the micro-op cache
    10.
    发明授权
    Method and apparatus for virtualizing the micro-op cache 有权

    公开(公告)号：US11586441B2

    公开(公告)日：2023-02-21

    申请号：US17125730

    申请日：2020-12-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Kalamatianos ,  Jagadish B. Kotra

    IPC: G06F9/38 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/30

    Abstract: Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.

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