公开(公告)号：US20210304673A1

公开(公告)日：2021-09-30

申请号：US17191009

申请日：2021-03-03

申请人： Apple Inc.

发明人： Shengkui Gao ,  Haifeng Li ,  Sinan Alousi ,  Marc Joseph DeVincentis ,  Yafei Bi ,  Hung Sheng Lin ,  Yi Qiao ,  Paolo Sacchetto ,  Weijun Yao ,  Pierre-Yves Emelie ,  Maofeng Yang ,  Yue Jack Chu

IPC分类号： G09G3/3233

摘要： A system may include an electronic display panel having pixels, where each pixel may emit light based on a respective programming signal. The system may include a memory storing a map. The processing circuitry may determine a function for each pixel from the map. The processing circuitry may determine a respective control signal based on the function and a target brightness level for each pixel to generate multiple control signals, where the respective control signal is used to generate the respective programing signal for each pixel. The processing circuitry may determine a scaling factor based at least in part on the first map and may scale at least a subset of the multiple control signals based at least in part on the scaling factor.

公开(公告)号：US20190086992A1

公开(公告)日：2019-03-21

申请号：US16028199

申请日：2018-07-05

申请人： Apple Inc.

发明人： Hung Sheng Lin ,  Hyunwoo Nho ,  Hyunsoo Kim ,  Shengkui Gao ,  Chun Lu ,  Sinan Alousi ,  Chin-Wei Lin ,  Jesse Aaron Richmond ,  Yafei Bi ,  Injae Hwang ,  Haifeng Li ,  Mohammad Hajirostam

IPC分类号： G06F1/32 ,  G09G3/3258

摘要： An electronic display includes an active area having an array of pixels. The electronic display also includes multiple data power rails coupled to the active area that supply power to the array of pixels. The electronic display further includes data driving circuitry coupled to the multiple data power rails that drive the array of pixels. The electronic display also includes a controller coupled to the data driving circuitry having a processor. The processor causes the array of pixels to emit light based on a display brightness value. The processor also causes a pixel of the array of pixels to emit light at a brightness of gray level 0 by dynamically adjusting a data power rail of the multiple data power rails.

公开(公告)号：US10360826B2

公开(公告)日：2019-07-23

申请号：US15273458

申请日：2016-09-22

申请人： Apple Inc.

发明人： Yafei Bi ,  Xiaofeng Wang ,  Haifeng Li ,  Mohammad B. Vahid Far ,  Hopil Bae ,  Hung Shen Lin ,  Hyunwoo Nho ,  Wei H. Yao

IPC分类号： G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  G09G3/00

摘要： An electronic device includes one or more unit pixels with a first node, a second node, and a third node. The device includes light-emitting-diode (LED) voltage (Vled) sensing circuitry, that senses Vled of the one or more unit pixels, by: sampling a charge of a capacitor of the one or more unit pixels, transitioning from the sampling, and reading out the Vled based upon a change in the charge of the capacitor, such that an operation of the unit pixel may be modified based upon the Vled.

公开(公告)号：US10235927B2

公开(公告)日：2019-03-19

申请号：US15367143

申请日：2016-12-01

申请人： Apple Inc.

发明人： Haifeng Li ,  Kingsuk Brahma ,  Yafei Bi

IPC分类号： G09G3/36 ,  G09G3/20

摘要： Aspects of the subject technology relate to electronic devices with displays. A display may include display control circuitry including an internal oscillator and one or more counters. The counters may be used to calibrate a display line time to a system line time to ensure that each displayed frame is synchronized with received display data frames from system circuitry for the electronic device. The counters may include a first counter that maintains a current-row count during operation of a current row of display pixels during a current display frame and a second counter that maintains a current-frame count that indicates a number of counts accumulated during the current display frame. The current-row count and the current-frame count may be referenced to the system line time during operation of each pixel row to remove any errors accumulated during operation of the previous pixel rows.

公开(公告)号：US20190027114A1

公开(公告)日：2019-01-24

申请号：US15716708

申请日：2017-09-27

申请人： Apple Inc.

发明人： Yue Jack Chu ,  Christopher P. Tann ,  Arthur L. Spence ,  Brad W. Simeral ,  Yafei Bi ,  Jiayi Jin ,  Ruo-Gu Huang ,  Haifeng Li ,  Weijun Yao ,  Chaohao Wang

IPC分类号： G09G5/00 ,  G06T1/60 ,  G09G5/36

摘要： In situations with reduced image changes, display panels, such as the ones disclosed herein, may reduce their power consumption by performing self-refresh cycles, in which they may display locally stored data in the display panel instead of retrieving it from an image buffer. Methods and circuitry for management of the self-refresh cycle may reduce jitter, luminance errors, and/or flickers that may be caused by untimely self-refresh cycles that may occur as a result of latency in the image buffer. In some implementations, the display panel may have a dedicated low latency input that notifies an arrival of an incoming image. In some implementations, the self-refresh cycles of the panel may be managed by a host or a buffer that is responsible for sending the images.

公开(公告)号：US20180322823A1

公开(公告)日：2018-11-08

申请号：US15711696

申请日：2017-09-21

申请人： Apple Inc.

发明人： Sinan Alousi ,  Haifeng Li ,  Mohammad Hajirostam ,  Yafei Bi

IPC分类号： G09G3/20

CPC分类号： G09G3/2096 ,  G09G3/3208 ,  G09G3/36 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/043 ,  G09G2360/12

摘要： Systems and methods for improving perceived image quality of an electronic display communicatively coupled to an image data source that outputs a synchronization control signal, which indicates when an image frame is expected to stop being written, based on a source clock signal. The electronic display includes a display pixel row, a display driver, and a timing controller. The timing controller determines a target scan time to be used to write the image frame to the display pixel row and instructs the display driver to write the image frame to the display pixel row based on the target scan time and a display block signal, in which the timing controller instructs the display driver to continue writing the image frame to display pixel row after the electronic display receives the synchronization control signal when the synchronization control signal is received before the target scan time is reached.