公开(公告)号：US20240077930A1

公开(公告)日：2024-03-07

申请号：US17929932

申请日：2022-09-06

Applicant: Apple Inc.

Inventor： Joseph F Alverson ,  Brad W. Simeral ,  Daniel J. Drusch ,  Daniel P. Kumar ,  Derek J. DiCarlo ,  Ricky Wai Kit Yuen ,  Roberto G. Yepez ,  Shashi K. Dua ,  Ardra Singh ,  Gabrielle Andrea Badie Belzberg ,  Kartik Venkatraman ,  Gierad Laput ,  Archana Venkatesh ,  Jingran Zhou

IPC: G06F1/3234 ,  G06F1/3206

CPC classification number: G06F1/3265 ,  G06F1/3206

Abstract: The present disclosure describes systems and methods associated with selective powering of an electronic display in response to operating conditions, additional data, and/or predicting that the electronic display is not going to be viewed or visible. By selectively enabling the electronic display between power states based on a prediction of when a viewer is expected to view the electronic display, a perceivably always-on electronic display may be provided without the electronic display being always-on, thereby balancing consumer interests with technical requirements of a relatively long battery life and correspondingly low power consumption.

公开(公告)号：US20230082091A1

公开(公告)日：2023-03-16

申请号：US17934976

申请日：2022-09-23

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/3287 ,  G06F1/3228

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US20230014545A1

公开(公告)日：2023-01-19

申请号：US17949834

申请日：2022-09-21

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Peter F. Holland ,  Rohit K. Gupta ,  Brad W. Simeral

IPC: G06F1/3234 ,  G09G3/20 ,  G06F1/3218 ,  G06F1/18

Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

公开(公告)号：US11500448B2

公开(公告)日：2022-11-15

申请号：US17015288

申请日：2020-09-09

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3228 ,  H04B17/318

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US10224873B1

公开(公告)日：2019-03-05

申请号：US15377004

申请日：2016-12-13

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Rashed Mahameed ,  Brad W. Simeral

IPC: H02K33/18 ,  H02N2/18 ,  H03B5/12

Abstract: In various embodiments, a voltage collection bootstrap circuit includes a capacitor, an inductor, an oscillator, a bias circuit, and a switch. A current may be induced in the inductor, the oscillator, or both. The inductor, the oscillator, or both may store energy in the capacitor. The inductor, capacitor, and oscillator may supply energy to the bias circuit. The bias circuit may output a difference between a reference voltage and a voltage corresponding to the energy received from at least one of the inductor, capacitor, and oscillator. Based on the output of the bias circuit, a switch may connect the voltage collection circuit to an output of at least one of the inductor, capacitor, and oscillator. Accordingly, energy may be provided to the voltage collection circuit using one or more induced currents.

公开(公告)号：US20250068229A1

公开(公告)日：2025-02-27

申请号：US18908018

申请日：2024-10-07

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/3287 ,  G06F1/3228 ,  H04B17/318

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US20240094797A1

公开(公告)日：2024-03-21

申请号：US18476547

申请日：2023-09-28

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/3287 ,  G06F1/3228

CPC classification number: G06F1/3287 ,  G06F1/3228 ,  H04B17/318

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US20240019522A1

公开(公告)日：2024-01-18

申请号：US18353252

申请日：2023-07-17

Applicant: Apple Inc.

Inventor： Siddharth S. Hazra ,  Brad W. Simeral ,  Oleg Naroditsky ,  Lukas Polok ,  Adam S. Howell ,  Mehrad Tavakoli

IPC: G01S5/00 ,  H04W64/00 ,  G01S5/02

CPC classification number: G01S5/019 ,  H04W64/00 ,  G01S5/02585

Abstract: Performing a combination localization technique includes determining a target localization parameter, selecting a combination localization technique in accordance with the target localization parameter, including a first localization technique associated with a first power error time profile, and a second localization technique associated with a second power error time profile. A device location is determined using the first localization technique for a first time period in accordance with the first power error time profile, and an updated device location is determined using the second localization technique in response to a triggering condition. A further updated device location is determined using the first localization technique following the first time period based on the updated device location. At least one of a combined energy value and a combined maximum error rate for the combination localization technique satisfies the target localization parameter.

公开(公告)号：US10942559B2

公开(公告)日：2021-03-09

申请号：US16123848

申请日：2018-09-06

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Brad W. Simeral ,  Lior Zimet

IPC: G06F1/3234 ,  G06F1/3293 ,  G06F1/329

Abstract: An electronic device may include a display panel to display images based on corresponding image data and an image source to pre-render a flip-book including a first image frame for display at a first target presentation time and a second image frame for display at a second target presentation time. The electronic device may also include a display pipeline coupled between the display panel and the image source having image data processing circuitry to process image data for display. The electronic device may also include a controller to instruct the display pipeline to process image data, to determine a power-on time based on a target presentation time, and to instruct the display pipeline to power-gate the image data processing circuitry upon completion of the processing of image data and until the power-on time is reached.

公开(公告)号：US20170208690A1

公开(公告)日：2017-07-20

申请号：US15275369

申请日：2016-09-24

Applicant: Apple Inc.

Inventor： Paul A. Martinez ,  Curtis C. Mead ,  Scott D. Morrison ,  Giancarlo F. De La Cruz ,  Lin Chen ,  Albert Wang ,  Brad W. Simeral ,  Vu Vo ,  Wyeman Chen

IPC: H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H01G4/228 ,  H01G4/38 ,  H01G4/005 ,  H01G2/06 ,  H05K3/30 ,  H01G4/40

Abstract: Systems and methods described in this disclosure are related to fabrication and utilization of two-terminal electrical components that may have terminations with reduced width. Components, such as the ones described herein may be used to increase the density of components in electrical devices, as they may reduce a separation distance between devices that lead to solder bridging. Methods for fabrication are also described, including the use of ceramic layers that may provide reduction in parasitic capacitance and/or inductances.