公开(公告)号：US20140181571A1

公开(公告)日：2014-06-26

申请号：US13726437

申请日：2012-12-24

Applicant: APPLE INC.

Inventor： Jason M. Kassoff ,  Kevin C. Wong ,  Brian P. Lilly ,  Gurjeet S. Saund

IPC: G06F1/06

CPC classification number: G06F5/06 ,  G06F13/38 ,  G06F13/382

Abstract: Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction.

Abstract translation: 用于管理总线结构中快速到慢速链接的系统和方法。 一对链路接口单元连接具有时钟不匹配的代理。 每个链路接口单元包括用于存储通过时钟域穿越发送的事务的异步FIFO。 当新的事务的命令准备好发送，而前一个事务的数据仍然被发送时，链接接口单元阻止发送先前事务的最后数据节拍。 相反，在一个或多个时钟周期的延迟之后，最后的数据跳转与新事务的命令重叠。