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1.发明申请Interfacing Dynamic Hardware Power Managed Blocks and Software Power Managed Blocks 有权动态硬件电源管理块和软件电源管理块的接口公开(公告)号：US20140173307A1
公开(公告)日：2014-06-19
申请号：US13719535
申请日：2012-12-19
Applicant: APPLE INC.
Inventor： Erik P. Machnicki , Gurjeet S. Saund , Munetoshi Fukami , Shane J. Keil , Chaitanya Kosaraju , Erdem Guleyupoglu , Jason M. Kassoff , Kevin C. Wong
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3206 , G06F1/3246 , G06F1/329 , G06F1/3293 , Y02D10/24 , Y02D50/20
Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.
Abstract translation: 公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。 在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。 功能单元可以通过硬件，软件或两者进行功率管理。 每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。 链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。 响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。
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公开(公告)号：US20220083343A1
公开(公告)日：2022-03-17
申请号：US17532072
申请日：2021-11-22
Applicant: Apple Inc.
Inventor： Aditya Kesiraju , Andrew J. Beaumont-Smith , Brian P. Lilly , James Vash , Jason M. Kassoff , Krishna C. Potnuru , Rajdeep L. Bhuyar , Ran A. Chachick , Tyler J. Huberty , Derek R. Kumar
Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.
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公开(公告)号：US09170768B2
公开(公告)日：2015-10-27
申请号：US13726437
申请日：2012-12-24
Applicant: Apple Inc.
Inventor： Jason M. Kassoff , Kevin C. Wong , Brian P. Lilly , Gurjeet S. Saund
CPC classification number: G06F5/06 , G06F13/38 , G06F13/382
Abstract: Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction.
Abstract translation: 用于管理总线结构中快速到慢速链接的系统和方法。 一对链路接口单元连接具有时钟不匹配的代理。 每个链路接口单元包括用于存储通过时钟域穿越发送的事务的异步FIFO。 当新事务的命令准备好发送，而前一个事务的数据仍然被发送时，链接接口单元阻止发送先前事务的最后数据节拍。 相反，在一个或多个时钟周期的延迟之后，最后的数据跳转与新事务的命令重叠。
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公开(公告)号：US09541984B2
公开(公告)日：2017-01-10
申请号：US13910584
申请日：2013-06-05
Applicant: Apple Inc.
Inventor： Shih-Chieh R. Wen , Jason M. Kassoff , Wei-Han Lien
CPC classification number: G06F1/3228 , G06F1/3206 , G06F1/3275 , G06F1/3278 , Y02D10/14 , Y02D10/157
Abstract: A system and a method which include one or more processors, a memory coupled to at least one of the processors, a communication link coupled to the memory, and a power management unit. The power management unit may be configured to detect an inactive state of at least one of the processors. The power management unit may be configured to disable the communication link at a time after the processor enters the inactive state, and disable the memory at another time after the processor enters the inactive state.
Abstract translation: 包括一个或多个处理器，耦合到至少一个处理器的存储器，耦合到存储器的通信链路和电源管理单元的系统和方法。 电源管理单元可以被配置为检测至少一个处理器的不活动状态。 电源管理单元可以被配置为在处理器进入非活动状态之后的一个时间禁用通信链路，并且在处理器进入非活动状态之后的另一时间禁用该存储器。
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5.发明申请Interfacing Dynamic Hardware Power Managed Blocks and Software Power Managed Blocks 审中-公开动态硬件电源管理块和软件电源管理块的接口公开(公告)号：US20160026234A1
公开(公告)日：2016-01-28
申请号：US14876922
申请日：2015-10-07
Applicant: Apple Inc.
Inventor： Erik P. Machnicki , Gurjeet S. Saund , Munetoshi Fukami , Shane J. Keil , Chaitanya Kosaraju , Erdem Guleyupoglu , Jason M. Kassoff , Kevin C. Wong
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3206 , G06F1/3246 , G06F1/329 , G06F1/3293 , Y02D10/24 , Y02D50/20
Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.
Abstract translation: 公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。 在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。 功能单元可以通过硬件，软件或两者进行功率管理。 每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。 链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。 响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。
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Patent Agency Ranking
公开(公告)号：US09639143B2
公开(公告)日：2017-05-02
申请号：US14876922
申请日：2015-10-07
Applicant: Apple Inc.
Inventor： Erik P. Machnicki , Gurjeet S. Saund , Munetoshi Fukami , Shane J. Keil , Chaitanya Kosaraju , Erdem Guleyupoglu , Jason M. Kassoff , Kevin C. Wong
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3206 , G06F1/3246 , G06F1/329 , G06F1/3293 , Y02D10/24 , Y02D50/20
Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.
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公开(公告)号：US20140365798A1
公开(公告)日：2014-12-11
申请号：US13910584
申请日：2013-06-05
Applicant: Apple Inc.
Inventor： Shih-Chieh R. Wen , Jason M. Kassoff , Wei-Han Lien
IPC: G06F1/32
CPC classification number: G06F1/3228 , G06F1/3206 , G06F1/3275 , G06F1/3278 , Y02D10/14 , Y02D10/157
Abstract: A system and a method which include one or more processors, a memory coupled to at least one of the processors, a communication link coupled to the memory, and a power management unit. The power management unit may be configured to detect an inactive state of at least one of the processors. The power management unit may be configured to disable the communication link at a time after the processor enters the inactive state, and disable the memory at another time after the processor enters the inactive state.
Abstract translation: 包括一个或多个处理器，耦合到至少一个处理器的存储器，耦合到存储器的通信链路和电源管理单元的系统和方法。 电源管理单元可以被配置为检测至少一个处理器的不活动状态。 电源管理单元可以被配置为在处理器进入非活动状态之后的一个时间禁用通信链路，并且在处理器进入非活动状态之后的另一时间禁用该存储器。
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公开(公告)号：US11768690B2
公开(公告)日：2023-09-26
申请号：US17532072
申请日：2021-11-22
Applicant: Apple Inc.
Inventor： Aditya Kesiraju , Andrew J. Beaumont-Smith , Brian P. Lilly , James Vash , Jason M. Kassoff , Krishna C. Potnuru , Rajdeep L. Bhuyar , Ran A. Chachick , Tyler J. Huberty , Derek R. Kumar
CPC classification number: G06F9/3877 , G06F9/3009 , G06F9/3836 , G06F9/3863 , G06F9/3881 , G06F9/4887 , G06F11/3024 , G06F9/3879
Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.
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公开(公告)号：US11210104B1
公开(公告)日：2021-12-28
申请号：US17018963
申请日：2020-09-11
Applicant: Apple Inc.
Inventor： Aditya Kesiraju , Andrew J. Beaumont-Smith , Brian P. Lilly , James Vash , Jason M. Kassoff , Krishna C. Potnuru , Rajdeep L. Bhuyar , Ran A. Chachick , Tyler J. Huberty , Derek R. Kumar
Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.
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公开(公告)号：US10157137B1
公开(公告)日：2018-12-18
申请号：US14861470
申请日：2015-09-22
Applicant: Apple Inc.
Inventor： Prashant Jain , Jason M. Kassoff , Sandeep Gupta
IPC: G06F12/08 , G06F12/0864 , G06F3/06
Abstract: Techniques are disclosed relating to set-associative caches in processors. In one embodiment, an integrated circuit is disclosed that includes a set-associative cache configured to receive a request for a data block stored in one of a plurality of ways within the cache, the request specifying an address, a portion of which is a tag value. In such an embodiment, the integrated circuit includes a way prediction circuit configured to predict, based on the tag value, a way in which the requested data block is stored. The integrated circuit further includes a tag array circuit configured to perform a comparison of a portion of the tag value with a set of previously stored tag portions corresponding to the plurality of ways. The tag array circuit is further configured to determine whether the request hits in the cache based on the predicted way and an output of the comparison.
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