公开(公告)号：US20230359557A1

公开(公告)日：2023-11-09

申请号：US18353830

申请日：2023-07-17

Applicant: Apple Inc.

Inventor： Sandeep Gupta ,  Brian P. Lilly ,  Krishna C. Potnuru

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: A cache may include multiple request handling pipes, each of which may further include multiple request buffers, for storing device requests from one or more processors to one or more devices. Some of the device requests may require to be sent to the devices according to an order. For a given one of such device requests, the cache may select a request handling pipe, based on an address indicated by the device request, and select a request buffer, based on the available entries of the request buffers of the selected request handling pipe, to store the device request. The cache may further use a first-level and a second-level token stores to track and maintain the device requests in order when transmitting the device requests to the devices.

公开(公告)号：US20160055099A1

公开(公告)日：2016-02-25

申请号：US14929645

申请日：2015-11-02

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

公开(公告)号：US20150309944A1

公开(公告)日：2015-10-29

申请号：US14263386

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Brian P. Lilly ,  Hari S. Kannan

IPC: G06F12/12

CPC classification number: G06F12/122 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041

Abstract: A method and apparatus for evicting cache lines from a cache memory includes receiving a request from one of a plurality of processors. The cache memory is configured to store a plurality of cache lines, and a given cache line includes an identifier indicating a processor that performed a most recent access of the given cache line. The method further includes selecting a cache line for eviction from a group of least recently used cache lines, where each cache line of the group of least recently used cache lines occupy a priority position less that a predetermined value, and then evicting the selected cache line.

Abstract translation: 用于从高速缓冲存储器中取出高速缓存行的方法和装置包括从多个处理器之一接收请求。 高速缓存存储器被配置为存储多条高速缓存行，并且给定的高速缓存行包括指示执行给定高速缓存行的最近访问的处理器的标识符。 该方法还包括从一组最近最少使用的高速缓存行中选择用于逐出的高速缓存行，其中最近最少使用的高速缓存行的组中的每个高速缓存行占据优先级位置小于预定值，然后逐出所选择的高速缓存行 。

公开(公告)号：US20150026404A1

公开(公告)日：2015-01-22

申请号：US13946327

申请日：2013-07-19

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。

公开(公告)号：US20140119146A1

公开(公告)日：2014-05-01

申请号：US13663946

申请日：2012-10-30

Applicant: APPLE INC.

Inventor： Brian P. Lilly

IPC: G11C5/14

CPC classification number: G11C7/22

Abstract: A storage array and a method of operating the same are disclosed. A storage array includes a number of clocked storage circuits arranged in rows and columns. The storage array is subdivided into a number of grids each including a subset of clocked storage circuits and also includes a number of clock gating circuits, each of which is coupled to provide a clock signal to the clocked storage circuits of a corresponding subset. During an access of the storage array (i.e. a read or a write), one of the clock gating circuits is configured to provide the clock signal to the clocked storage circuits of its correspondingly coupled subset. The remaining clock gating circuits are configured to inhibit the clock signal from being provided to the flop circuits of their respectively coupled subsets.

Abstract translation: 公开了一种存储阵列及其操作方法。 存储阵列包括以行和列布置的多个时钟存储电路。 存储阵列被细分为多个网格，每个栅格包括时钟存储电路的子集，并且还包括多个时钟门控电路，每个时钟门控电路被耦合以向相应子集的时钟控制的存储电路提供时钟信号。 在存储阵列的访问期间（即，读或写）期间，其中一个时钟选通电路被配置为将时钟信号提供给其对应耦合子集的定时存储电路。 剩余的时钟门控电路被配置为禁止将时钟信号提供给它们分别耦合的子集的触发器电路。

公开(公告)号：US20130103906A1

公开(公告)日：2013-04-25

申请号：US13709649

申请日：2012-12-10

Applicant: Apple Inc.

Inventor： Peter J. Bannon ,  Andrew J. Beaumont-Smith ,  Ramesh B. Gunna ,  Wei-han Lien ,  Brian P. Lilly ,  Jaidev P. Patwardhan ,  Shih-Chieh R. Wen ,  Tse-Yu Yeh

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804

Abstract: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

Abstract translation: 在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。 组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。 例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为“折叠”。 折叠的写缓冲器条目及其中的折叠写入操作可以包括至少一个写入操作，该写入操作已经覆盖由缓冲器条目中的先前写入操作写入的数据。 在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

公开(公告)号：US11893241B1

公开(公告)日：2024-02-06

申请号：US17823695

申请日：2022-08-31

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Sandeep Gupta ,  Chandan Shantharaj ,  Krishna C. Potnuru ,  Sahil Kapoor

IPC: G06F3/06 ,  G06F12/0877

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0877 ,  G06F2212/60

Abstract: A variable latency cache memory is disclosed. A cache subsystem includes a pipeline control circuit configured to initiate cache memory accesses for data. The cache subsystem further includes a cache memory circuit having a data array arranged into a plurality of groups, wherein different ones of the plurality of groups have different minimum access latencies due to different distances from the pipeline control circuit. A plurality of latency control circuits configured to ensure a latency is bounded to a maximum value for a given access to the data array, wherein a given latency control circuit is associated with a corresponding group of the plurality of groups. The latency for a given access may thus vary between a minimum access latency for a group closest to the pipeline control circuit to a maximum latency for an access to the group furthest from the pipeline control circuit.

公开(公告)号：US20220083472A1

公开(公告)日：2022-03-17

申请号：US17315725

申请日：2021-05-10

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund

IPC: G06F12/0815

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：US09563575B2

公开(公告)日：2017-02-07

申请号：US14929645

申请日：2015-11-02

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。

公开(公告)号：US09563567B2

公开(公告)日：2017-02-07

申请号：US14263369

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Mahnaz P Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Brian P. Lilly ,  Hari S Kannan

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A method and apparatus for selectively powering down a portion of a cache memory includes determining a power down condition dependent upon a number of accesses to the cache memory. In response to the detection of the power down condition, selecting a group of cache ways included in the cache memory dependent upon a number of cache lines in each cache way that are also included in another cache memory. The method further includes locking and flushing the selected group of cache ways, and then activating a low power mode for the selected group of cache ways.

Abstract translation: 用于选择性地降低高速缓存存储器的一部分的方法和装置包括根据对高速缓冲存储器的访问次数确定掉电条件。 响应于断电状态的检测，根据还包括在另一个高速缓冲存储器中的每种高速缓存方式中的高速缓存行数量，选择包括在高速缓冲存储器中的一组高速缓存路。 该方法还包括锁定和刷新所选择的一组高速缓存路径，然后激活所选择的高速缓存路径组的低功率模式。