公开(公告)号：US09740645B2

公开(公告)日：2017-08-22

申请号：US14691244

申请日：2015-04-20

Applicant: Apple Inc.

Inventor： Michael W. Murphy ,  Joshua P. de Cesare ,  Timothy R. Paaske

IPC: G06F13/24 ,  G06F1/32

CPC classification number: G06F13/24 ,  G06F1/3253 ,  Y02D10/151

Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

公开(公告)号：US09015396B2

公开(公告)日：2015-04-21

申请号：US13622266

申请日：2012-09-18

Applicant: Apple Inc.

Inventor： Michael W. Murphy ,  Joshua P. de Cesare ,  Timothy R. Paaske

IPC: G06F13/24 ,  G06F1/32 ,  G06F1/00

CPC classification number: G06F13/24 ,  G06F1/3253 ,  Y02D10/151

Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。