公开(公告)号：US20210202334A1

公开(公告)日：2021-07-01

申请号：US16731365

申请日：2019-12-31

Applicant: APPLIED MATERIALS, INC.

Inventor： PENG SUO ,  PRAYUDI LIANTO ,  GUAN HUEI SEE ,  ARVIND SUNDARRAJAN ,  LIT PING LAM ,  PANGYEN ONG ,  OLIVIA KOENTJORO ,  WEI-SHENG LEI ,  JUNGRAE PARK

IPC: H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L23/367

Abstract: A method of forming a semiconductor structure on a wafer includes depositing a polymer layer on the wafer in a wafer-level packaging process, forming at least one wafer-level packaging structure in the polymer layer using a direct writing process that alters a chemical property of portions of the polymer layer that have been directly written to, and removing portions of the polymer layer that have not been written to by the direct writing process revealing the at least one wafer-level packaging structure. In some embodiments, the direct writing process is a two-photon polymerization process that uses a femtosecond laser in combination with a pair of galvanometric laser scanners to solidify portions of the polymer layer to form the wafer-level packaging structure.

公开(公告)号：US20190287898A1

公开(公告)日：2019-09-19

申请号：US16296929

申请日：2019-03-08

Applicant: APPLIED MATERIALS, INC.

Inventor： PENG SUO ,  YU GU ,  GUAN HUEI SEE ,  ARVIND SUNDARRAJAN

IPC: H01L23/525

Abstract: Methods and apparatus for forming an embedded antifuse in a wafer-level packaging compatible process. In some embodiments, a method for forming an embedded antifuse includes forming a first redistribution layer on a first polymer layer, depositing an antifuse dielectric layer on the first redistribution layer, forming a second polymer layer on the antifuse dielectric layer, creating at least one first via through the second polymer layer to the antifuse dielectric layer using a lithography process with, for example, a dielectric etch, and forming a second redistribution layer on the second polymer layer and contacting the antifuse dielectric layer at a bottom of the at least one first via.

公开(公告)号：US20190181092A1

公开(公告)日：2019-06-13

申请号：US15835909

申请日：2017-12-08

Applicant: APPLIED MATERIALS, INC.

Inventor： CHIEN-KANG HSIUNG ,  ARVIND SUNDARRAJAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/66

Abstract: A wafer-level bridge die is affixed with an adhesive layer to a redistribution layer (RDL) that has been temporarily bonded to a carrier. Electrical interconnects are formed on the RDL and on the bridge die and encapsulated in a first mold layer. A plurality of dies are coupled to the RDL and the bridge die such that a die is electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die. A second mold layer is formed on the first mold layer to encapsulate the plurality of dies. The temporary bond is then broken and the carrier is removed, exposing the RDL connections.

公开(公告)号：US20190006223A1

公开(公告)日：2019-01-03

申请号：US15638798

申请日：2017-06-30

Applicant: APPLIED MATERIALS, INC.

Inventor： GUAN HUEI SEE ,  YU GU ,  ARVIND SUNDARRAJAN

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Methods and apparatus for wafer level packaging are described herein. According to one embodiment, a method comprises depositing an adhesive layer atop a carrier, placing at least a portion of a substrate pre-fabricated with a plurality of die cavities and a plurality of through vias atop the laminate, inserting a die into each of the die cavities, encapsulating the die and the substrate and debonding and removing the laminate and the carrier from the encapsulated die and substrate. Another embodiment provides an apparatus comprising a substrate, a plurality of die cavities formed through the substrate and a plurality of conductive through vias disposed through the substrate and arranged about the perimeter of each die cavity, wherein a top surface of the substrate is exposed for application of an encapsulating layer and a bottom surface of the substrate is exposed for placement on an adhesive layer.

公开(公告)号：US20180350732A1

公开(公告)日：2018-12-06

申请号：US15664954

申请日：2017-07-31

Applicant: APPLIED MATERIALS, INC.

Inventor： YU GU ,  GUAN HUEI SEE ,  ARVIND SUNDARRAJAN

IPC: H01L23/498 ,  H01L21/48

Abstract: A method of processing a substrate includes depositing a polymer layer atop the substrate to cover an exposed conductive layer on the substrate; curing the polymer layer; forming a patterned masking layer atop the cured polymer layer; etching an exposed portion of the polymer layer through the patterned masking layer to form a via through the polymer layer to a top surface of the conductive layer; and removing the patterned masking layer.