公开(公告)号：US20200097289A1

公开(公告)日：2020-03-26

申请号：US16468098

申请日：2017-11-10

Applicant: ARM LIMITED

Inventor： Jacob EAPEN ,  Grigorios MAGKLIS ,  Mbou EYOLE

IPC: G06F9/30

Abstract: In response to a replicate partition instruction specifying partition information defining positions of a plurality of variable size partitions within a result vector, an instruction decoder (20) controls the processing circuitry (80) to generate a result vector in which each partition having more than one data element comprises data values or element indices of a sequence of data elements of a source vector starting or ending at a selected data element position. This instruction can be useful for accelerating processing of data structures smaller than the vector length.

公开(公告)号：US20190012176A1

公开(公告)日：2019-01-10

申请号：US15748734

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Grigorios MAGKLIS ,  Alejandro MARTINEZ VICENTE ,  Nathanael PREMILLIEU ,  Mbou EYOLE

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/3836

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of a data vector comprising a plurality of data items at respective positions in the data vector, according to the state of respective predicate flags associated with the positions; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a WHILE instruction and a CHANGE instruction, to control the instruction processing dependent upon a number of the predicate flags.

公开(公告)号：US20180196673A1

公开(公告)日：2018-07-12

申请号：US15741303

申请日：2016-06-23

Applicant: ARM Limited

Inventor： Nigel John STEPHENS ,  Grigorios MAGKLIS ,  Alejandro MARTINEZ VICENTE ,  Nathanael PREMILLIEU

IPC: G06F9/30

Abstract: A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. The scaling vector length querying instructions may be in the form of count instructions, increment instructions or decrement instructions. The instructions may include a pattern constraint applying a constraint, such as modulo(M) or power of 2 to the partial result value representing the number of vector elements provided for the register element size specified for the instruction.