公开(公告)号：US20180358086A1

公开(公告)日：2018-12-13

申请号：US15619332

申请日：2017-06-09

Applicant: ARM Limited

Inventor： Ankur Goel ,  Saikat Kumar Banik ,  Lokesh Kumar Saini ,  Vivek Asthana

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/11 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418 ,  H01L23/528 ,  H01L27/1104

Abstract: A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.