公开(公告)号：US20170365331A1

公开(公告)日：2017-12-21

申请号：US15188873

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Mohit Chanana ,  Ankur Goel

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the memory cell via the complementary bitlines. The pair of write drivers may be arranged to provide the complementary bitline signals to the memory cell based on complementary boost signals. The device may include a pair of complementary boost generators coupled to corresponding gates of the pair of write drivers. The pair of complementary boost generators may be arranged to selectively provide the complementary boost signals to the corresponding gates of the pair of write drivers based on the at least one data bit value.

公开(公告)号：US10861534B2

公开(公告)日：2020-12-08

申请号：US16368246

申请日：2019-03-28

Applicant: Arm Limited

Inventor： Ankur Goel ,  Ishan Khera ,  Nimish Sharma ,  Ishita Satishchandra Desai ,  Vikash Kumar ,  Nitesh Gautam

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11 ,  G11C11/413

Abstract: The claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. Particularly, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.

公开(公告)号：US10854280B2

公开(公告)日：2020-12-01

申请号：US15691001

申请日：2017-08-30

Applicant: ARM Limited

Inventor： Abhairaj Singh ,  Vivek Asthana ,  Monu Rathore ,  Ankur Goel ,  Nikhil Kaushik ,  Rachit Ahuja ,  Rahul Mathur ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C11/408 ,  G11C11/419 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

公开(公告)号：US10515684B2

公开(公告)日：2019-12-24

申请号：US15823490

申请日：2017-11-27

Applicant: Arm Limited

Inventor： Mohit Chanana ,  Ankur Goel ,  Shruti Aggarwal

IPC: G11C11/413 ,  G11C11/408 ,  G11C11/418 ,  G11C11/419 ,  G11C8/08

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The wordline driver may include multiple transistors. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. Gates of the read assist transistor and at least one transistor of the multiple transistors may be coupled together. While activated, the read assist transistor may provide a read assist signal to the wordline when the wordline is selected and driven by the wordline driver.

公开(公告)号：US09997217B1

公开(公告)日：2018-06-12

申请号：US15477516

申请日：2017-04-03

Applicant: ARM Limited

Inventor： Ankur Goel ,  Munish Kumar ,  Nitin Jindal ,  Rahul Mathur ,  Shruti Aggarwal ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/16 ,  G11C8/18 ,  G11C7/20

CPC classification number: G11C7/12 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.

公开(公告)号：US20200312403A1

公开(公告)日：2020-10-01

申请号：US16368246

申请日：2019-03-28

Applicant: Arm Limited

Inventor： Ankur Goel ,  Ishan Khera ,  Nimish Sharma ,  Ishita Satishchandra Desai ,  Vikash Kumar ,  Nitesh Gautam

IPC: G11C11/419

Abstract: Briefly, embodiments of claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. In particular embodiments, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.

公开(公告)号：US20190164590A1

公开(公告)日：2019-05-30

申请号：US15823490

申请日：2017-11-27

Applicant: Arm Limited

Inventor： Mohit Chanana ,  Ankur Goel ,  Shruti Aggarwal

IPC: G11C11/408 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The wordline driver may include multiple transistors. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. Gates of the read assist transistor and at least one transistor of the multiple transistors may be coupled together. While activated, the read assist transistor may provide a read assist signal to the wordline when the wordline is selected and driven by the wordline driver.

公开(公告)号：US20190066772A1

公开(公告)日：2019-02-28

申请号：US15691001

申请日：2017-08-30

Applicant: ARM Limited

Inventor： Abhairaj Singh ,  Vivek Asthana ,  Monu Rathore ,  Ankur Goel ,  Nikhil Kaushik ,  Rachit Ahuja ,  Rahul Mathur ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

公开(公告)号：US10199094B2

公开(公告)日：2019-02-05

申请号：US15619332

申请日：2017-06-09

Applicant: ARM Limited

Inventor： Ankur Goel ,  Saikat Kumar Banik ,  Lokesh Kumar Saini ,  Vivek Asthana

IPC: G11C11/412 ,  G11C11/419 ,  H01L23/528 ,  H01L27/11 ,  G11C11/418

Abstract: A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.

公开(公告)号：US10199092B2

公开(公告)日：2019-02-05

申请号：US15188873

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Mohit Chanana ,  Ankur Goel

IPC: G11C11/00 ,  G11C11/419

Abstract: Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the memory cell via the complementary bitlines. The pair of write drivers may be arranged to provide the complementary bitline signals to the memory cell based on complementary boost signals. The device may include a pair of complementary boost generators coupled to corresponding gates of the pair of write drivers. The pair of complementary boost generators may be arranged to selectively provide the complementary boost signals to the corresponding gates of the pair of write drivers based on the at least one data bit value.