公开(公告)号：US20190267049A1

公开(公告)日：2019-08-29

申请号：US15904292

申请日：2018-02-23

Applicant: Arm Limited

Inventor： Vivek Asthana ,  Nitin Jindal ,  Saikat Kumar Banik

IPC: G11C7/06 ,  G11C8/12 ,  G11C8/06 ,  G11C7/10

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

公开(公告)号：US10199094B2

公开(公告)日：2019-02-05

申请号：US15619332

申请日：2017-06-09

Applicant: ARM Limited

Inventor： Ankur Goel ,  Saikat Kumar Banik ,  Lokesh Kumar Saini ,  Vivek Asthana

IPC: G11C11/412 ,  G11C11/419 ,  H01L23/528 ,  H01L27/11 ,  G11C11/418

Abstract: A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.

公开(公告)号：US20180358086A1

公开(公告)日：2018-12-13

申请号：US15619332

申请日：2017-06-09

Applicant: ARM Limited

Inventor： Ankur Goel ,  Saikat Kumar Banik ,  Lokesh Kumar Saini ,  Vivek Asthana

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/11 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418 ,  H01L23/528 ,  H01L27/1104

Abstract: A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.

公开(公告)号：US20200342916A1

公开(公告)日：2020-10-29

申请号：US16397677

申请日：2019-04-29

Applicant: Arm Limited

Inventor： Amit Chhabra ,  Saikat Kumar Banik

IPC: G11C5/14 ,  G11C11/417

Abstract: Various implementations described herein are directed to an integrated circuit that has memory circuitry with a memory structure and a reference path. The integrated circuit includes performance sensing circuitry having a logic structure that is adapted to detect variation of performance of the memory structure. The integrated circuit includes power management circuitry that is coupled to the memory circuitry and the performance sensing circuitry. The power management circuitry receives a feedback signal from the performance sensing circuitry and adaptively adjusts voltage provided to the memory circuitry based on the feedback signal to affect performance of the memory structure. The memory circuitry has a logic stage that reduces signal delay in the reference path for alignment with the adaptively adjusted voltage.

公开(公告)号：US10418124B1

公开(公告)日：2019-09-17

申请号：US15904292

申请日：2018-02-23

Applicant: Arm Limited

Inventor： Vivek Asthana ,  Nitin Jindal ,  Saikat Kumar Banik

IPC: G11C7/06 ,  G11C29/00 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12 ,  G11C29/56 ,  G11C29/28 ,  G11C16/04 ,  G11C29/12 ,  G11C29/14

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

公开(公告)号：US10217743B2

公开(公告)日：2019-02-26

申请号：US15434659

申请日：2017-02-16

Applicant: ARM Limited

Inventor： Akshay Kumar ,  Saikat Kumar Banik

IPC: G11C11/00 ,  H01L27/092 ,  G11C29/00 ,  G11C5/02 ,  G11C11/417

Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array disposed in a first area of the integrated circuit. The memory cell array may include memory cells with first transistors of multiple types. The integrated circuit may include a process sensor disposed in a second area of the integrated circuit that is different than the first area. The process sensor may include a process detector having second transistors of the multiple types that are separate from the first transistors. The second transistors of the process detector may be arranged for detecting process variation of the memory cells of the memory cell array.