公开(公告)号：US11106465B2

公开(公告)日：2021-08-31

申请号：US16650999

申请日：2018-11-15

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Nigel John Stephens ,  Neil Burgess ,  Grigorios Magklis

IPC: G06F9/30 ,  G06F7/50

Abstract: Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.

公开(公告)号：US10430192B2

公开(公告)日：2019-10-01

申请号：US15748734

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Grigorios Magklis ,  Alejandro Martinez Vicente ,  Nathanael Premillieu ,  Mbou Eyole

IPC: G06F9/30 ,  G06F9/38

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of a data vector comprising a plurality of data items at respective positions in the data vector, according to the state of respective predicate flags associated with the positions; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a WHILE instruction and a CHANGE instruction, to control the instruction processing dependent upon a number of the predicate flags.

公开(公告)号：US11481290B2

公开(公告)日：2022-10-25

申请号：US17046396

申请日：2019-04-08

Applicant: Arm Limited

Inventor： Matthew James Horsnell ,  Grigorios Magklis ,  Stephan Diestelhorst

IPC: G06F11/00 ,  G06F11/14 ,  G06F9/46 ,  G06F11/07

Abstract: An apparatus and a method of operating a data processing apparatus, and simulators thereof, are disclosed. Data processing circuitry performs data processing operations in response to instructions, where some sets of instructions may be defined as a transaction which are to be performed atomically with respect to other operations performed by the data processing circuitry. When a synchronous exception occurs during a transaction the transaction is aborted and an exception counter is incremented. When the counter reaches a threshold value a transaction failure signal is generated, allowing, if appropriate a response to this number of exceptions causing transaction aborts to be carried out.

公开(公告)号：US11422807B2

公开(公告)日：2022-08-23

申请号：US16629178

申请日：2018-06-27

Applicant: ARM LIMITED

Inventor： Grigorios Magklis ,  Nigel John Stephens

IPC: G06F9/30

Abstract: An apparatus and method of operating an apparatus are provided. The apparatus is responsive to a bit-testing instruction which specifies a source vector register and an index to perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits. The bit-testing procedure comprises, for each processed element of the plural elements, setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index. This bit-testing instruction thus enables increased performance of program code which is required to perform multiple bit tests and can be suitably formulated into a vectorised form.

公开(公告)号：US10824350B2

公开(公告)日：2020-11-03

申请号：US16309190

申请日：2017-05-18

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Grigorios Magklis

IPC: G06F3/06 ,  G06F21/79 ,  G06F12/14 ,  G06F12/1027 ,  G06F9/30 ,  G06F12/10

Abstract: A data processing apparatus and method serve to manage access permission checking in respect of contingent memory access operations (the access permission failure of which does not alter program flow) in dependence of a contingent-access permission checking disable flag. If the contingent access disable flag has a first value, then this disables memory permission circuitry e.g. a walk state machine 22, from performing a check as to whether or not the memory access circuitry is permitted to perform a requested memory access. Non-contingent memory accesses are able to utilise the memory permission circuitry irrespective of the value of the contingent-access permission checking disable flag.