公开(公告)号：US20210334373A1

公开(公告)日：2021-10-28

申请号：US16855716

申请日：2020-04-22

Applicant: Arm Limited

Inventor： Subbayya Chowdary YANAMADALA ,  Jeremy Patrick DUBEUF ,  Carl Wayne VINEYARD ,  Matthias Lothar BOETTCHER ,  Hugo John Martin VINCENT ,  Shidhartha DAS

IPC: G06F21/56 ,  G06F9/54 ,  G06F21/72 ,  G06F21/85

Abstract: A moderator system that can receive outputs of various stages of the security analytic framework and can receive input from external sources to provide information about emerging styles of attacks. One or more models/behavioral profiles can be curated by the moderator system, and the moderator system can provide updates to components of the security analytics framework.

公开(公告)号：US20210294748A1

公开(公告)日：2021-09-23

申请号：US16825021

申请日：2020-03-20

Applicant: Arm Limited

Inventor： Matthias Lothar BOETTCHER

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/14 ,  G06F12/02 ,  G06F12/0864 ,  G06F9/30

Abstract: There is provided a data processing apparatus that includes memory circuitry that provides a physical address space, which is logically divided into a plurality of memory segments and stores a plurality of accessors with associated validity indicators. Each of the accessors controls access to a region of the physical address space in dependence on at least its associated validity indicator. Tracking circuitry tracks which of the memory segments contain the accessors and invalidation circuitry responds to a request to invalidate an accessor by determining a set of equivalent accessors with reference to the tracking circuitry, and invalidating the accessor and the equivalent accessors by setting the associated validity indicator of each of the accessor and the equivalent accessors to indicate that the accessor and the equivalent accessors are invalid.

公开(公告)号：US20210232511A1

公开(公告)日：2021-07-29

申请号：US16975255

申请日：2020-06-24

Applicant: Arm Limited

Inventor： Matthias Lothar BOETTCHER ,  François Christopher Jacques BOTMAN

IPC: G06F12/14 ,  G06F12/02 ,  G06F12/1009

Abstract: An apparatus comprises capability checking circuitry 86 to perform a capability validity checking operation to determine whether use of a capability satisfies one or more use-limiting conditions. The capability comprises a pointer and pointer-use-limiting information specifying the one or more use-limiting conditions. The one or more use-limiting conditions comprise at least an allowable range of addresses for the pointer. In response to a capability write request requesting that a capability is written to a memory location associated with a capability write target address, when capability write address tracking is enabled, capability write address tracking circuitry 200 updates a capability write address tracking structure 100 based on the capability write target address.

公开(公告)号：US20210224042A1

公开(公告)日：2021-07-22

申请号：US16745808

申请日：2020-01-17

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Matthias Lothar BOETTCHER

IPC: G06F7/72

Abstract: An apparatus and method are provided for maintaining a counter value. The apparatus has first counter control circuitry for maintaining a first counter value representing a first portion of a hybrid counter value, and second counter control circuitry for maintaining a second counter value representing a second portion of the hybrid counter value, wherein the second portion is a higher order portion of the hybrid counter value than the first portion. The first counter control circuitry is arranged to maintain the first counter value as a binary value that indicates a magnitude of the first counter value, the first counter control circuitry comprising adder circuitry that is responsive to an adjustment value to update the first counter value by performing an addition operation to add the adjustment value to a current binary value of the first counter value, and to generate a carry out signal which is set when a carry out is generated by the addition operation. The second counter control circuitry is arranged to maintain the second counter value as a bit sequence having N discrete states, and is responsive to the carry out signal being set to transition the second counter value from the current discrete state to a new discrete state. This allows an arbitrary value to be used as the adjustment value, that is smaller than or equal to the maximum value of the first counter, whilst avoiding the need for the generation and handling of carry bits to be managed across the entire bit range of the hybrid counter value.

公开(公告)号：US20210058237A1

公开(公告)日：2021-02-25

申请号：US16546596

申请日：2019-08-21

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Matthias Lothar BOETTCHER ,  Prakash S. RAMRAKHYANI

IPC: H04L9/06 ,  H04L9/32 ,  G06F12/14 ,  G06F21/72 ,  G06F13/16

Abstract: An apparatus and method are described, the apparatus comprising memory control circuitry configured to control access to data stored in memory, and memory security circuitry configured to generate encrypted data to be stored in the memory, the encrypted data being based on target data and a first one-time-pad (OTP). In response to an OTP update event indicating that the first OTP is to be updated to a second OTP different to the first OTP, the memory security circuitry is configured to generate a re-encryption value based on the first OTP and the second OTP, and the memory security circuitry is configured to issue a re-encryption request to cause updated encrypted data to be generated in a downstream component based on the encrypted data and the re-encryption value and to cause the encrypted data to be replaced in the memory by the updated encrypted data.