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    DYNAMIC SELECTION OF MEMORY MANAGEMENT ALGORITHM
    4.
    发明申请
    DYNAMIC SELECTION OF MEMORY MANAGEMENT ALGORITHM 有权
    动态选择存储器管理算法

    公开(公告)号：US20150355851A1

    公开(公告)日：2015-12-10

    申请号：US14300735

    申请日：2014-06-10

    Applicant: ARM Limited

    Inventor： Christopher Neal HINDS ,  Steven D. KRUEGER ,  Carl Wayne VINEYARD

    IPC: G06F3/06

    CPC classification number: G06F3/0617 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/467 ,  G06F13/1663

    Abstract: A data processing system 2 includes a memory controller 20 which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.

    Abstract translation: 数据处理系统2包括存储器控制器20，其从多个候选管理算法动态地选择要用于管理存储器访问冲突的所选择的管理算法。 存储器管理算法可以包括使用存储器锁的推测存储器访问问题和/或存储器访问问题的各种版本。 基于检测到的系统状态参数进行动态选择。 这些检测到的状态参数可以包括冲突级指示符，诸如在全局，每进程，每区域或每个线程的一个或多个上跟踪的存储器访问冲突计数器。

    REPETITIVE SIDE CHANNEL ATTACK COUNTERMEASURES
    6.
    发明申请
    REPETITIVE SIDE CHANNEL ATTACK COUNTERMEASURES 审中-公开

    公开(公告)号：US20200012822A1

    公开(公告)日：2020-01-09

    申请号：US16030459

    申请日：2018-07-09

    Applicant: Arm Limited

    Inventor： Carl Wayne VINEYARD ,  Christopher Neal HINDS ,  Adeline-Fleur FLEMING

    IPC: G06F21/77 ,  G06F21/72 ,  G06F21/56

    Abstract: A computing device incorporating repetitive side channel attack (SCA) countermeasures can include a timer circuit and a capacitive delay circuit that notifies of a potential repetitive-based attack by sending an activity-detected signal that can be used to initiate an appropriate countermeasure response. Additionally, or independently, a computing device incorporating repetitive SCA countermeasures can include at least one storage unit that can store an incoming input signal, at least one comparator to compare the incoming input signal with another signal and indicate a match, and a counter that increments upon the match. When the counter reaches a specified limit, a limit-exceeded signal can be sent to notify of a potential repetitive-based attack and initiate an appropriate countermeasure response.

    TRACKING EVENTS OF INTEREST TO MITIGATE ATTACKS
    7.
    发明申请
    TRACKING EVENTS OF INTEREST TO MITIGATE ATTACKS 审中-公开

    公开(公告)号：US20200012783A1

    公开(公告)日：2020-01-09

    申请号：US16409205

    申请日：2019-05-10

    Applicant: Arm Limited

    Inventor： Carl Wayne VINEYARD ,  Christopher Neal HINDS ,  Subbayya Chowdary YANAMADALA ,  Asaf SHEN

    IPC: G06F21/55 ,  G06F21/56

    Abstract: A computing device can include a comparator coupled to an I/O pin of the computing device; a storage unit coupled to the comparator; and a counter coupled to receive an output of the comparator, an output of the counter being coupled to a computation engine to provide a limit-exceeded signal to the computation engine, wherein the counter comprises a volatile counter and a nonvolatile storage, wherein the nonvolatile storage stores a bit for each top volatile count number of events identified by the volatile counter. The computing device can further include a backup power source coupled to the volatile counter; and readout circuitry and control logic coupled to the volatile counter and to the nonvolatile storage, the readout circuitry and control logic being configured to control operations of the volatile counter during an error event and determine a total number of events. The computing device can be a smart card.

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