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公开(公告)号:US20210334373A1
公开(公告)日:2021-10-28
申请号:US16855716
申请日:2020-04-22
Applicant: Arm Limited
Inventor: Subbayya Chowdary YANAMADALA , Jeremy Patrick DUBEUF , Carl Wayne VINEYARD , Matthias Lothar BOETTCHER , Hugo John Martin VINCENT , Shidhartha DAS
Abstract: A moderator system that can receive outputs of various stages of the security analytic framework and can receive input from external sources to provide information about emerging styles of attacks. One or more models/behavioral profiles can be curated by the moderator system, and the moderator system can provide updates to components of the security analytics framework.
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公开(公告)号:US20180336372A1
公开(公告)日:2018-11-22
申请号:US15967900
申请日:2018-05-01
Applicant: Arm Limited
Inventor: Adeline-Fleur FLEMING , Carl Wayne VINEYARD , George McNeil LATTIMORE , Christopher Neal HINDS , Robert John HARRISON , Mikael RIEN , Abdellah BAKHALI , Robert Christiaan SCHOUTEN , Jean-Charles BOLINHAS
CPC classification number: H02J7/0068 , H01L27/00 , H02J7/0054 , H02J7/345
Abstract: Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.
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公开(公告)号:US20180337767A1
公开(公告)日:2018-11-22
申请号:US15600974
申请日:2017-05-22
Applicant: ARM Limited
Inventor: Robert John HARRISON , Mikael RIEN , Carl Wayne VINEYARD , George McNeil LATTIMORE , Christopher Neal HINDS , Adeline-Fleur FLEMING
Abstract: Power is received from a first power signal a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.
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公开(公告)号:US20150355851A1
公开(公告)日:2015-12-10
申请号:US14300735
申请日:2014-06-10
Applicant: ARM Limited
Inventor: Christopher Neal HINDS , Steven D. KRUEGER , Carl Wayne VINEYARD
IPC: G06F3/06
CPC classification number: G06F3/0617 , G06F3/0658 , G06F3/0659 , G06F3/0673 , G06F9/467 , G06F13/1663
Abstract: A data processing system 2 includes a memory controller 20 which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.
Abstract translation: 数据处理系统2包括存储器控制器20,其从多个候选管理算法动态地选择要用于管理存储器访问冲突的所选择的管理算法。 存储器管理算法可以包括使用存储器锁的推测存储器访问问题和/或存储器访问问题的各种版本。 基于检测到的系统状态参数进行动态选择。 这些检测到的状态参数可以包括冲突级指示符,诸如在全局,每进程,每区域或每个线程的一个或多个上跟踪的存储器访问冲突计数器。
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公开(公告)号:US20210334415A1
公开(公告)日:2021-10-28
申请号:US16855659
申请日:2020-04-22
Applicant: Arm Limited
Inventor: Subbayya Chowdary YANAMADALA , Jeremy Patrick DUBEUF , Carl Wayne VINEYARD , Matthias Lothar BOETTCHER , Hugo John Martin VINCENT , Shidhartha DAS
Abstract: Analytics processing circuitry can include a data scavenger and a data analyzer coupled to receive the data from the data scavenger. The data scavenger collects data from at least one element of interest of a plurality of elements of interest of an IC. The data analyzer identifies patterns in the data from the data scavenger over a time frame or for a snapshot of time based on a predefined metric. The analytics processing circuitry can further include a moderator and a risk predictor. The risk predictor generates a risk assessment regarding whether the data collected by the data scavenger is indicative of normal behavior or abnormal behavior based at least on the output of the data analyzer and a behavioral model for the IC, which can be device and application specific. A threat response can be performed based on the risk assessment.
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公开(公告)号:US20200012822A1
公开(公告)日:2020-01-09
申请号:US16030459
申请日:2018-07-09
Applicant: Arm Limited
Inventor: Carl Wayne VINEYARD , Christopher Neal HINDS , Adeline-Fleur FLEMING
Abstract: A computing device incorporating repetitive side channel attack (SCA) countermeasures can include a timer circuit and a capacitive delay circuit that notifies of a potential repetitive-based attack by sending an activity-detected signal that can be used to initiate an appropriate countermeasure response. Additionally, or independently, a computing device incorporating repetitive SCA countermeasures can include at least one storage unit that can store an incoming input signal, at least one comparator to compare the incoming input signal with another signal and indicate a match, and a counter that increments upon the match. When the counter reaches a specified limit, a limit-exceeded signal can be sent to notify of a potential repetitive-based attack and initiate an appropriate countermeasure response.
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公开(公告)号:US20200012783A1
公开(公告)日:2020-01-09
申请号:US16409205
申请日:2019-05-10
Applicant: Arm Limited
Abstract: A computing device can include a comparator coupled to an I/O pin of the computing device; a storage unit coupled to the comparator; and a counter coupled to receive an output of the comparator, an output of the counter being coupled to a computation engine to provide a limit-exceeded signal to the computation engine, wherein the counter comprises a volatile counter and a nonvolatile storage, wherein the nonvolatile storage stores a bit for each top volatile count number of events identified by the volatile counter. The computing device can further include a backup power source coupled to the volatile counter; and readout circuitry and control logic coupled to the volatile counter and to the nonvolatile storage, the readout circuitry and control logic being configured to control operations of the volatile counter during an error event and determine a total number of events. The computing device can be a smart card.
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