公开(公告)号：US20090172215A1

公开(公告)日：2009-07-02

申请号：US12006247

申请日：2007-12-31

申请人： Mamun Ur Rashid

发明人： Mamun Ur Rashid

IPC分类号： G06F13/00

CPC分类号： G06F13/4059 ,  Y02D10/14 ,  Y02D10/151

摘要： Methods and apparatus to odd and even frame combination data path architectures are described. In one embodiment, a logic may include a buffer and a parallel input, serial output (PISO) logic that may be utilized for transferring data between a source and a destination. The logic may be utilized for transferring the data whether or not the data is transmitted in accordance with single ended or differential signals. Other embodiments are also described.

摘要翻译： 描述了奇数和偶数帧组合数据路径架构的方法和装置。 在一个实施例中，逻辑可以包括可用于在源和目的地之间传送数据的缓冲器和并行输入串行输出（PISO）逻辑。 逻辑可以用于传送数据，无论数据是根据单端还是差分信号发送的。 还描述了其它实施例。

公开(公告)号：US07061224B2

公开(公告)日：2006-06-13

申请号：US10949583

申请日：2004-09-24

申请人： Akira Kakizawa ,  Mark Beiley ,  Mamun Ur Rashid

发明人： Akira Kakizawa ,  Mark Beiley ,  Mamun Ur Rashid

IPC分类号： G01R23/175 ,  H03L7/06

CPC分类号： H03L7/0812 ,  G01R25/005 ,  H03L7/0805

摘要： A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the input signal. The method further comprises generating a test output signal from the input signal and delay lock loop output signal indicative of a relationship between a transition on the input signal and a transition on delay lock loop output signal.

公开(公告)号：US07805627B2

公开(公告)日：2010-09-28

申请号：US11729627

申请日：2007-03-29

申请人： Mamun Ur Rashid ,  Hing Y. To

发明人： Mamun Ur Rashid ,  Hing Y. To

IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F1/14

CPC分类号： G06F1/08

摘要： A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.

摘要翻译： 一种技术包括提供各自与总线的数据位线相关联的发射机，并且每个发射机由相关联的发射时钟信号计时。 该技术包括确定应用于基本时钟信号的基线偏移以使基本时钟信号与向发送器提供数据的源的源时钟信号同步。 对于每个发射机，确定相关联的相位偏移以补偿相关联的偏移。 每个传输时钟信号的相位根据相关的相位偏移和基线偏移量进行控制。

公开(公告)号：US07590789B2

公开(公告)日：2009-09-15

申请号：US11999929

申请日：2007-12-07

申请人： Mamun Ur Rashid

发明人： Mamun Ur Rashid

IPC分类号： G06F13/00 ,  G06F1/12

CPC分类号： G06F13/4081 ,  Y02D10/14 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct receipt of the predetermined data pattern in a buffer of the second agent, determining in a state machine of the first agent an updated load position within a window of the predetermined data pattern at which the buffer can realize the correct receipt, and transmitting the updated load position to the second agent to enable the second agent to capture incoming data from the first agent at the updated load position. Other embodiments are described and claimed.

公开(公告)号：US20080244298A1

公开(公告)日：2008-10-02

申请号：US11729627

申请日：2007-03-29

申请人： Mamun Ur Rashid ,  Hing Y. To

发明人： Mamun Ur Rashid ,  Hing Y. To

IPC分类号： G06F1/12

CPC分类号： G06F1/08

摘要： A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.

摘要翻译： 一种技术包括提供各自与总线的数据位线相关联的发射机，并且每个发射机由相关联的发射时钟信号计时。 该技术包括确定应用于基本时钟信号的基线偏移以使基本时钟信号与向发送器提供数据的源的源时钟信号同步。 对于每个发射机，确定相关联的相位偏移以补偿相关联的偏移。 每个传输时钟信号的相位根据相关的相位偏移和基线偏移量进行控制。

公开(公告)号：US20090150586A1

公开(公告)日：2009-06-11

申请号：US11999929

申请日：2007-12-07

申请人： Mamun Ur Rashid

发明人： Mamun Ur Rashid

IPC分类号： G06F13/00

CPC分类号： G06F13/4081 ,  Y02D10/14 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct receipt of the predetermined data pattern in a buffer of the second agent, determining in a state machine of the first agent an updated load position within a window of the predetermined data pattern at which the buffer can realize the correct receipt, and transmitting the updated load position to the second agent to enable the second agent to capture incoming data from the first agent at the updated load position. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于将预定数据模式从第一代理发送到接口的第二代理的方法，在第二代理的缓冲器中接收预定数据模式的正确接收的指示， 所述第一代理的状态机在所述预定数据模式的窗口内的更新的加载位置处，所述缓冲器可以在该窗口内实现正确的接收，并且将更新的加载位置发送到第二代理，以使得第二代理能够从第一代理捕获输入数据 代理在更新的加载位置。 描述和要求保护其他实施例。

公开(公告)号：US07388795B1

公开(公告)日：2008-06-17

申请号：US11647656

申请日：2006-12-28

申请人： Hing To ,  Mamun Ur Rashid

发明人： Hing To ,  Mamun Ur Rashid

IPC分类号： G11C7/00

CPC分类号： H03L7/0812 ,  H03L7/0805

摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes a phase locked loop (PLL) to generate a differential reference clock and a first clocking component coupled to the PLL. The first clocking component includes a first delay locked loop (DLL) to receive the reference clock and to generate transmit and receive delay de-skew clock signals, a first set of phase interpolators to provide data transmit de-skewing and a first set of slave delay lines to provide data receive de-skewing.

摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括产生差分参考时钟的锁相环（PLL）和耦合到PLL的第一时钟元件。 第一时钟元件包括接收参考时钟并产生发射和接收延迟去偏移时钟信号的第一延迟锁定环路（DLL），提供数据发射去偏移的第一组相位内插器和第一组从站 延迟线提供数据接收去偏移。

公开(公告)号：US07109768B2

公开(公告)日：2006-09-19

申请号：US10881003

申请日：2004-06-29

申请人： Mamun Ur Rashid

发明人： Mamun Ur Rashid

IPC分类号： H03K5/12

CPC分类号： H03K5/12 ,  H03K19/017581

摘要： A device includes an output circuit to output an output signal. The device also includes a control loop circuit to measure the real slew of the output signal. The control loop circuit compares the real slew with a target slew adjusts the output circuit when the real slew and the target are mismatched.

摘要翻译： 一种装置包括输出电路以输出输出信号。 该装置还包括一个控制回路电路，用于测量输出信号的实际转速。 控制回路电路将实际转速与目标转速进行比较，当实际转速和目标不匹配时，调整输出电路。