公开(公告)号：US11934827B2

公开(公告)日：2024-03-19

申请号：US17556291

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sooraj Puthoor ,  Muhammad Amber Hassaan ,  Ashwin Aji ,  Michael L. Chu ,  Nuwan Jayasena

IPC: G06F9/30 ,  G06F7/575 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F7/575 ,  G06F9/3001 ,  G06F9/3856

Abstract: An apparatus that manages multi-process execution in a processing-in-memory (“PIM”) device includes a gatekeeper configured to: receive an identification of one or more registered PIM processes; receive, from a process, a memory request that includes a PIM command; if the requesting process is a registered PIM process and another registered PIM process is active on the PIM device, perform a context switch of PIM state between the registered PIM processes; and issue the PIM command of the requesting process to the PIM device.

公开(公告)号：US11868306B2

公开(公告)日：2024-01-09

申请号：US17943527

申请日：2022-09-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Chu ,  Ashwin Aji ,  Muhammad Amber Hassaan

IPC: G06F15/78

CPC classification number: G06F15/7821

Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.

公开(公告)号：US20230099163A1

公开(公告)日：2023-03-30

申请号：US17943527

申请日：2022-09-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Chu ,  Ashwin Aji ,  Muhammad Amber Hassaan

IPC: G06F15/78

Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.