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公开(公告)号：US11468001B1
公开(公告)日：2022-10-11
申请号：US17217792
申请日：2021-03-30
IPC分类号： G06F15/78
摘要： A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.
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公开(公告)号：US11868809B2
公开(公告)日：2024-01-09
申请号：US18095704
申请日：2023-01-11
发明人： Muhammad Amber Hassaan , Anirudh Mohan Kaushik , Sooraj Puthoor , Gokul Subramanian Ravi , Bradford Beckmann , Ashwin Aji
IPC分类号： G06F9/46 , G06F9/48 , G06F9/52 , G06F16/901
CPC分类号： G06F9/4881 , G06F9/52 , G06F16/9024 , G06F2209/486
摘要： A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.
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公开(公告)号：US11720993B2
公开(公告)日：2023-08-08
申请号：US16138708
申请日：2018-09-21
CPC分类号： G06T1/60 , G06F9/30098 , G06F12/02 , G06F12/023 , G06T1/20
摘要： A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.
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公开(公告)号：US11934827B2
公开(公告)日：2024-03-19
申请号：US17556291
申请日：2021-12-20
CPC分类号： G06F9/3004 , G06F7/575 , G06F9/3001 , G06F9/3856
摘要： An apparatus that manages multi-process execution in a processing-in-memory (“PIM”) device includes a gatekeeper configured to: receive an identification of one or more registered PIM processes; receive, from a process, a memory request that includes a PIM command; if the requesting process is a registered PIM process and another registered PIM process is active on the PIM device, perform a context switch of PIM state between the registered PIM processes; and issue the PIM command of the requesting process to the PIM device.
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公开(公告)号：US11868306B2
公开(公告)日：2024-01-09
申请号：US17943527
申请日：2022-09-13
IPC分类号： G06F15/78
CPC分类号： G06F15/7821
摘要： A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.
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公开(公告)号：US20230099163A1
公开(公告)日：2023-03-30
申请号：US17943527
申请日：2022-09-13
IPC分类号： G06F15/78
摘要： A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.
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公开(公告)号：US12019560B2
公开(公告)日：2024-06-25
申请号：US17556431
申请日：2021-12-20
IPC分类号： G06F12/10 , G06F12/02 , G06F12/1009 , G06F12/1045 , G06F12/1072 , G06F13/16
CPC分类号： G06F12/1072 , G06F12/0238 , G06F12/1009 , G06F12/1054 , G06F12/1063 , G06F13/1673 , G06F2212/7201
摘要： Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.
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公开(公告)号：US11934698B2
公开(公告)日：2024-03-19
申请号：US17556503
申请日：2021-12-20
CPC分类号： G06F3/0659 , G06F3/0622 , G06F3/0631 , G06F3/0656 , G06F3/0679 , G06F7/575
摘要： Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.
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公开(公告)号：US11734059B2
公开(公告)日：2023-08-22
申请号：US16824601
申请日：2020-03-19
发明人： Muhammad Amber Hassaan , Anirudh Mohan Kaushik , Sooraj Puthoor , Gokul Subramanian Ravi , Bradford Beckmann , Ashwin Aji
IPC分类号： G06F9/46 , G06F9/48 , G06F9/52 , G06F16/901
CPC分类号： G06F9/4881 , G06F9/52 , G06F16/9024 , G06F2209/486
摘要： A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.
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公开(公告)号：US20230196502A1
公开(公告)日：2023-06-22
申请号：US18103322
申请日：2023-01-30
CPC分类号： G06T1/60 , G06F9/30098 , G06F12/023 , G06T1/20 , G06F12/02
摘要： A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.
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