公开(公告)号：US11513802B2

公开(公告)日：2022-11-29

申请号：US17033883

申请日：2020-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. Boyer ,  John Kalamatianos ,  Pritam Majumder

IPC: G06F9/38 ,  G06F9/22

Abstract: An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.

公开(公告)号：US10282295B1

公开(公告)日：2019-05-07

申请号：US15825880

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Walker ,  Michael W. Boyer ,  Yasuko Eckert ,  Gabriel H. Loh

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/128

Abstract: A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of entries of the cache coherence directory. Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.