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    Data converter false saturation detector
    12.
    发明授权
    Data converter false saturation detector 有权

    公开(公告)号：US11275127B2

    公开(公告)日：2022-03-15

    申请号：US16715492

    申请日：2019-12-16

    Applicant: Allegro MicroSystems, LLC

    Inventor： Jay M. Towne ,  Peter Tengstrand ,  Devon Fernandez

    IPC: G01R33/00 ,  G01R35/00 ,  G01R33/02 ,  H03M3/00

    Abstract: According to aspects of the disclosure, an apparatus is disclosed comprising: a controller; an analog-to-digital converter (ADC) coupled to the controller, the ADC including an input terminal for receiving a sensor signal from a transducer; and a diagnostic circuit coupled to the input terminal of the ADC and to the controller, the diagnostic circuit being configured to: generate a diagnostic signal that indicates whether a voltage at the input terminal of the ADC meets a first threshold, and provide the diagnostic signal to the controller, wherein the controller is configured to: receive a data sample from the ADC, detect whether the data sample meets a second threshold, and transition the apparatus into a safe state when: (i) the diagnostic signal indicates that the voltage at the input terminal does not meet the first threshold, and (ii) the data sample meets the second threshold.

    Methods and apparatus for monitoring a level of a regulated source
    13.
    发明授权
    Methods and apparatus for monitoring a level of a regulated source 有权

    公开(公告)号：US11243234B2

    公开(公告)日：2022-02-08

    申请号：US17061602

    申请日：2020-10-02

    Applicant: Allegro MicroSystems, LLC

    Inventor： Sam Tran ,  Jay M. Towne ,  P. Karl Scheller

    IPC: G01R19/165 ,  G01R31/40 ,  G01R31/28 ,  G01R33/02 ,  G01D5/14

    Abstract: A monitor circuit for monitoring a level of a first and second regulated source may monitor a voltage level of regulated voltages or a current level of regulated currents. In an embodiment, the monitor circuit includes circuitry responsive to a first regulated current and to a second regulated current. A first circuit responsive to the first regulated current and to the second regulated current generates a first error signal indicative of at least one of an overcurrent condition of the first regulated current and an undercurrent condition of the second regulated current. A second circuit responsive to the first regulated current and to the second regulated current generates a second error signal indicative of at least one of an undercurrent condition of the first regulated current and an overcurrent condition of the second regulated current. A method for monitoring the levels of first and second regulated sources is also provided.

    Dual edge synchronization of analog input to reduce switch point jitter
    16.
    发明授权
    Dual edge synchronization of analog input to reduce switch point jitter 有权

    公开(公告)号：US10797851B2

    公开(公告)日：2020-10-06

    申请号：US15966572

    申请日：2018-04-30

    Applicant: Allegro MicroSystems, LLC

    Inventor： Jay M. Towne ,  Steven E. Snyder ,  Steven Ricco ,  Matthew Nealon

    IPC: H04L7/00 ,  G01D18/00 ,  G01J1/44 ,  G01K15/00 ,  G01R35/00

    Abstract: A method for synchronization of an input signal includes providing the input signal to a first signal path associated with a first clock and to a second signal path associated with a second clock, detecting an edge of the input signal by detecting values of the input signal along the first signal path at a first rising edge of the first clock and at a second rising edge of the first clock, detecting a value of the input signal along the second signal path at an edge of the second clock, and selecting the input signal from the first signal path or from the second signal path according to the detected value of the input signal along the second path when an edge of the input signal along the first path is detected.

    METHODS AND APPARATUS FOR MONITORING A LEVEL OF A REGULATED SOURCE
    17.
    发明申请
    METHODS AND APPARATUS FOR MONITORING A LEVEL OF A REGULATED SOURCE 审中-公开
    监测一个监管来源的方法和装置

    公开(公告)号：US20160377663A1

    公开(公告)日：2016-12-29

    申请号：US14748692

    申请日：2015-06-24

    Applicant: ALLEGRO MICROSYSTEMS, LLC

    Inventor： Jay M. Towne ,  Sam Tran ,  P. Karl Scheller

    IPC: G01R19/165 ,  G01R31/28 ,  G01R31/40

    CPC classification number: G01R19/165 ,  G01D5/145 ,  G01R31/28 ,  G01R31/40 ,  G01R33/02

    Abstract: A monitor circuit for monitoring a level of a first and second regulated source may monitor a voltage level of regulated voltages or a current level of regulated currents. In an embodiment, the monitor circuit includes circuitry responsive to a first regulated voltage and to a second regulated voltage. A first circuit responsive to the first regulated voltage and to the second regulated voltage generates a first error signal indicative of at least one of an overvoltage condition of the first regulated voltage and an undervoltage condition of the second regulated voltage. A second circuit responsive to the first regulated voltage and to the second regulated voltage generates a second error signal indicative of at least one of an undervoltage condition of the first regulated voltage and an overvoltage condition of the second regulated voltage. A method for monitoring the levels of first and second regulated sources is also provided.

    Abstract translation: 用于监测第一和第二调节源的电平的监视器电路可以监视调节电压的电压电平或电流的调节电流。 在一个实施例中，监视器电路包括响应于第一调节电压和第二调节电压的电路。 响应于第一调节电压和第二调节电压的第一电路产生指示第一调节电压的过电压状态和第二调节电压的欠压状态中的至少一个的第一误差信号。 响应于第一调节电压和第二调节电压的第二电路产生指示第一调节电压的欠压状态和第二调节电压的过电压状态中的至少一个的第二误差信号。 还提供了用于监测第一和第二调节源的水平的方法。

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