公开(公告)号：US07192853B1

公开(公告)日：2007-03-20

申请号：US10659421

申请日：2003-09-10

Applicant: Andrew Strachan ,  Vladislav Vashchenko

Inventor： Andrew Strachan ,  Vladislav Vashchenko

IPC: H01L21/04

CPC classification number: H01L29/36 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0615

Abstract: A method is provided for forming a graded junction in a semiconductor material having a first conductivity type. Dopant having a second conductivity type opposite the first conductivity type is introduced into a selected region of the semiconductor material to define a primary dopant region therein. The perimeter of the primary dopant region defines a primary pn junction. While introducing dopant into the selected region of the semiconductor material, dopant is simultaneously introduced into the semiconductor material around the perimeter of the primary dopant region and spaced-apart from the primary pn junction. The dopant in the both the primary dopant region and in the dopant around the perimeter of the primary dopant region is then diffused to provide a graded dopant region. The graded dopant region thus include an interior portion that has a first dopant gradient with a first maximum dopant concentration and a perimeter portion that is contiguous with the interior portion and has a second dopant gradient with a second maximum dopant concentration that is less than the first maximum dopant concentration.

Abstract translation: 提供了一种在具有第一导电类型的半导体材料中形成渐变结的方法。 具有与第一导电类型相反的第二导电类型的掺杂剂被引入到半导体材料的选定区域中以在其中限定主掺杂区域。 主要掺杂剂区域的周边限定了初级pn结。 当将掺杂剂引入到半导体材料的选定区域中时，掺杂剂同时被引入围绕主掺杂区域周边的半导体材料并且与初级pn结隔开。 然后，在主要掺杂区域的周围的主掺杂区域和掺杂剂两者中的掺杂剂被扩散以提供渐变掺杂区域。 渐变掺杂区域因此包括具有第一掺杂剂浓度的第一掺杂剂梯度和与内部部分邻接的周边部分的内部部分，并且具有第二掺杂剂梯度，其中第二最大掺杂剂浓度小于第一掺杂剂浓度 最大掺杂浓度。

公开(公告)号：US06798641B1

公开(公告)日：2004-09-28

申请号：US10647602

申请日：2003-08-25

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Andrew Strachan

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Andrew Strachan

IPC: H01G4228

CPC classification number: H01L27/0805 ,  H01L29/92

Abstract: A multiple-layer diffusion junction capacitor structure includes multiple layers of inter-digitated P-type dopant and N-type dopant formed in a semiconductor substrate. An opening in a hard mask is formed taking care to control the angle of the sidewall using a dry, anisotropic etching process. P-type and N-type dopant are then implanted at positive and negative shallow angles, respectively, each with a different energy and dose. By utilizing the properly determined implant angles, implant energies and implant doses for each of the dopant types, a high capacitance and high density diode junction capacitor, with inter-digitated N-type and P-type regions in the vertical direction is provided.

Abstract translation: 多层扩散结电容器结构包括在半导体衬底中形成的多层数字化P型掺杂剂和N型掺杂剂。 形成硬掩模的开口，其中形成了使用干燥的各向异性蚀刻工艺来控制侧壁的角度。 然后分别以正和负的浅角度注入P型和N型掺杂剂，每种具有不同的能量和剂量。 通过利用适当确定的植入角度，提供每种掺杂剂类型的注入能量和注入剂量，高电容和高密度二极管结电容器，在垂直方向上具有数字化的N型和P型区域。

公开(公告)号：US06646320B1

公开(公告)日：2003-11-11

申请号：US10301183

申请日：2002-11-21

Applicant: Andrew Strachan

Inventor： Andrew Strachan

IPC: H01L2900

CPC classification number: H01L29/66272 ,  H01L21/2257 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/763 ,  H01L21/8249

Abstract: Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An “emitter window” is masked directly over the polysilicon trench fill. Heavily doped single emitter poly is deposited and masked over the entire active region. The standard emitter drive then diffuses dopant through the emitter window into the undoped trench poly fill to provide an ohmic contact between the emitter poly and the trench poly fill. Contact to the emitter poly is made from overlying metal.

Abstract translation: 现有的多晶硅发射器技术用于接触多孔填充沟槽隔离结构。 遵循标准的单个多发射器窗口过程。 在多晶硅沟槽填充物上直接掩蔽“发射极窗口”。 重掺杂的单发射极聚合物在整个有源区上沉积并掩蔽。 然后，标准发射器驱动器将掺杂剂通过发射器窗口扩散到未掺杂的沟槽多晶硅填充物中，以在发射极多晶硅和沟槽多晶硅填充物之间提供欧姆接触。 与发射极接触是由金属制成。

公开(公告)号：US06548839B1

公开(公告)日：2003-04-15

申请号：US10079093

申请日：2002-02-20

Applicant: Andrew Strachan ,  Douglas Brisbin

Inventor： Andrew Strachan ,  Douglas Brisbin

IPC: H01L2710

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/41758

Abstract: An LDMOS array includes an array of alternating source regions and drain regions formed in a semiconductor substrate to define a checkerboard pattern of source and drain regions. A source contact is formed in electrical contact with each of the source regions in the array to connect the source regions in parallel. A drain contact is formed in electrical contact with each of the drain regions in the array to connect the drain regions in parallel. A drain ring is formed around the periphery of the checkerboard pattern and in electrical contact with the drain contact, providing redistribution of the current flow within the LDMOS array and thereby allowing safer hot carrier operation at higher biases than with the conventional layout.

Abstract translation: LDMOS阵列包括形成在半导体衬底中的交替源极区和漏极区的阵列，以限定源区和漏区的棋盘图案。 源极触点形成为与阵列中的每个源极区域电接触以平行地连接源极区域。 漏极接触形成为与阵列中的每个漏极区域电接触以平行地连接漏极区域。 排水环形成在棋盘图形的周边周围并与漏极接触电接触，提供电流在LDMOS阵列内的再分配，从而允许比传统布局更高的偏压更安全的热载体操作。

公开(公告)号：US08664076B2

公开(公告)日：2014-03-04

申请号：US13239192

申请日：2011-09-21

Applicant: Venkat Raghavan ,  Andrew Strachan

Inventor： Venkat Raghavan ,  Andrew Strachan

IPC: H01L21/20

CPC classification number: H01L28/90

Abstract: A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack and on exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.

Abstract translation: 形成电容器结构的方法包括：在下面的介电层上形成掺杂的多晶硅层; 在所述掺杂多晶硅层上形成电介质叠层; 在所述电介质堆叠中形成接触孔以暴露所述掺杂多晶硅层的表面区域; 形成填充所述接触孔并与所述掺杂多晶硅层的暴露表面接触的导电接触插塞; 在所述电介质堆叠中形成多个沟槽，使得每个沟槽暴露所述掺杂多晶硅层的对应表面区域; 在电介质堆叠的暴露表面和掺杂多晶硅层的暴露表面上形成导电底电容器板; 在底部电容器板上形成电容器电介质层; 以及在所述电容器介电层上形成导电顶部电容器板。

公开(公告)号：US07560348B2

公开(公告)日：2009-07-14

申请号：US11705975

申请日：2007-02-14

Applicant: Douglas Brisbin ,  Andrew Strachan

Inventor： Douglas Brisbin ,  Andrew Strachan

IPC: H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/7835

Abstract: A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

Abstract translation: 可以根据本发明设计和制造PMOS器件以定位其漏极结击穿点和最大冲击电离点，以减少或消除漏极击穿电压。 在一些实施例中，漏极结击穿点和最大冲击电离点位于距离栅极足够远的位置，器件不会显示出显着的漏极击穿电压。 该器件可以是具有包括P型轻掺杂漏极（P-LDD）注入的扩展漏极区域的高压功率晶体管，漏极结击穿和最大冲击电离点通过控制用于产生P的植入剂量来适当地定位 -LDD植入物。 本发明的其他方面是用于设计PMOS器件的方法，包括通过确定栅极的相对位置和漏极结击穿和最大冲击电离点中的至少一个来减少漏极击穿电压的走向，以及用于制造集成电路的方法，包括 本发明的PMOS器件的任何实施例。

公开(公告)号：US07510944B1

公开(公告)日：2009-03-31

申请号：US11801704

申请日：2007-05-10

Applicant: Venkat Raghavan ,  Andrew Strachan

Inventor： Venkat Raghavan ,  Andrew Strachan

IPC: H01L21/20

CPC classification number: H01L28/60

Abstract: In a method of forming MIM capacitor structure, a TiW layer is formed and a capacitor mask is used to define areas of the TiW layer that will be sued in the formation of the MIM capacitor. A capacitor mask is then used to expose surface areas of the TiW layer, followed by deposition of a capacitor dielectric layer. A via mask and etch are then performed to provide a contact via to the bottom plate TiW layer. After the via etch, a Ti/TiN liner stack is deposited. The Ti/TiN multilayer stacked film serves as the capacitor top plate as well as the via contact liner film. Next, Tungsten is deposited to fill the vias and a Tungsten planarization step is performed.

Abstract translation: 在形成MIM电容器结构的方法中，形成TiW层，并且使用电容器掩模来限定将在MIM电容器的形成中被起诉的TiW层的区域。 然后使用电容器掩模来暴露TiW层的表面区域，随后沉积电容器介电层。 然后进行通孔掩模和蚀刻，以向底板TiW层提供接触通孔。 在通孔蚀刻之后，沉积Ti / TiN衬垫堆叠。 Ti / TiN多层叠层膜用作电容器顶板以及通孔接触衬垫膜。 接下来，沉积钨以填充通孔，并执行钨平坦化步骤。

公开(公告)号：US07071513B1

公开(公告)日：2006-07-04

申请号：US10975171

申请日：2004-10-28

Applicant: Terry Dyer ,  Andrew Strachan

Inventor： Terry Dyer ,  Andrew Strachan

IPC: H01L29/72

CPC classification number: H01L29/7813 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

Abstract: An economical integration of trench VDMOS devices into a conventional BCD process is provided, with the optimization of key aspects of the device layout for low Rds(on) area. Specifically, trench orientation, array geometry, the number of source cells between drain pickups and drain-source spacing are independently optimized. In one embodiment of the invention, the optimized device utilizes a rectangular cell array with an elongation ratio in the range of 5/3–7/3, with a ratio of 5/3 being preferred, and a cell orientation at 45° with respect to the wafer flat on a 100 wafer.

Abstract translation: 提供了将沟槽VDMOS器件经济地集成到常规BCD工艺中，并优化了低R ds（on）区域的器件布局的关键方面。 具体地，沟槽取向，阵列几何形状，漏极拾取器之间的源极单元的数量和漏 - 源间隔是独立优化的。 在本发明的一个实施例中，优化的装置利用具有在5 / 3-7 / 3范围内的伸长比的矩形电池阵列，比例优选为5/3，电池取向相对于45° 在晶片上平坦地放置在100个晶圆上。