公开(公告)号：US08541863B2

公开(公告)日：2013-09-24

申请号：US12955061

申请日：2010-11-29

Applicant: Venkat Raghavan ,  Andrew Strachan

Inventor： Venkat Raghavan ,  Andrew Strachan

IPC: H01L21/70

CPC classification number: H01L29/78 ,  H01L27/11558 ,  H01L29/0619 ,  H01L29/7881

Abstract: An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region.

Abstract translation: 形成在半导体衬底上的电可编程只读存储器（EPROM）位单元结构包括形成在半导体衬底上的N型外延层，形成在外延层中的N型阱区，在外围形成的LOCOS场氧化物 在阱区中限定有源器件区的阱区，在有源区中形成的场氧化物环和与LOCOS场氧化物分开的空间以限定EPROM位单元区，以及形成在EPROM位中的EPROM位单元 细胞区域。

公开(公告)号：US08086979B2

公开(公告)日：2011-12-27

申请号：US12480916

申请日：2009-06-09

Applicant: Douglas Brisbin ,  Andrew Strachan

Inventor： Douglas Brisbin ,  Andrew Strachan

IPC: G06F17/50

CPC classification number: H01L29/0847 ,  H01L29/7835

Abstract: A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

Abstract translation: 可以根据本发明设计和制造PMOS器件以定位其漏极结击穿点和最大冲击电离点，以减少或消除漏极击穿电压。 在一些实施例中，漏极结击穿点和最大冲击电离点位于距离栅极足够远的位置，器件不会显示出显着的漏极击穿电压。 该器件可以是具有包括P型轻掺杂漏极（P-LDD）注入的扩展漏极区域的高压功率晶体管，漏极结击穿和最大冲击电离点通过控制用于产生P的植入剂量来适当地定位 -LDD植入物。 本发明的其他方面是用于设计PMOS器件的方法，包括通过确定栅极的相对位置和漏极结击穿和最大冲击电离点中的至少一个来减少漏极击穿电压的走向，以及用于制造集成电路的方法，包括 本发明的PMOS器件的任何实施例。

公开(公告)号：US20130069200A1

公开(公告)日：2013-03-21

申请号：US13239192

申请日：2011-09-21

Applicant: Venkat Raghavan ,  Andrew Strachan

Inventor： Venkat Raghavan ,  Andrew Strachan

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/90

Abstract: A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilsicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack an don exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.

Abstract translation: 形成电容器结构的方法包括：在下面的介电层上形成掺杂的多晶硅层; 在所述掺杂多晶硅层上形成电介质叠层; 在所述电介质堆叠中形成接触孔以暴露所述掺杂聚硅氧烷层的表面区域; 形成填充所述接触孔并与所述掺杂多晶硅层的暴露表面接触的导电接触插塞; 在所述电介质堆叠中形成多个沟槽，使得每个沟槽暴露所述掺杂多晶硅层的对应表面区域; 在所述电介质堆叠的暴露表面上形成导电底部电容器板，以及所述掺杂多晶硅层的暴露表面; 在底部电容器板上形成电容器电介质层; 以及在所述电容器介电层上形成导电顶部电容器板。

公开(公告)号：US20120132975A1

公开(公告)日：2012-05-31

申请号：US12955061

申请日：2010-11-29

Applicant: Venkat Raghavan ,  Andrew Strachan

Inventor： Venkat Raghavan ,  Andrew Strachan

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L27/11558 ,  H01L29/0619 ,  H01L29/7881

Abstract: An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region.

Abstract translation: 形成在半导体衬底上的电可编程只读存储器（EPROM）位单元结构包括形成在半导体衬底上的N型外延层，形成在外延层中的N型阱区，在外围形成的LOCOS场氧化物 在阱区中限定有源器件区的阱区，在有源区中形成的场氧化物环和与LOCOS场氧化物分开的空间以限定EPROM位单元区，以及形成在EPROM位中的EPROM位单元 细胞区域。

公开(公告)号：US07425741B1

公开(公告)日：2008-09-16

申请号：US11186442

申请日：2005-07-21

Applicant: Andrew Strachan ,  Natalia Lavrovskaya ,  Saurabh Desai ,  Roozbeh Parsa ,  Yuri Mirgorodski

Inventor： Andrew Strachan ,  Natalia Lavrovskaya ,  Saurabh Desai ,  Roozbeh Parsa ,  Yuri Mirgorodski

IPC: H01L29/788

CPC classification number: H01L29/4234 ,  H01L21/28273 ,  H01L29/66825

Abstract: A biased conductive plate is provided over an NVM cell structure to overcome data retention charge loss due to the presence of dielectric films that are conductive at higher temperatures. The biased conductive plate is preferably formed from the lowest metal layer in the fabrication process flow, but any biased conductive layer can be used.

Abstract translation: 在NVM单元结构上提供偏置的导电板以克服由于在较高温度下导电的介电膜的存在而导致的数据保持电荷损失。 偏置的导电板优选地由制造工艺流程中的最低金属层形成，但是可以使用任何偏置的导电层。

公开(公告)号：US08445353B1

公开(公告)日：2013-05-21

申请号：US12586836

申请日：2009-09-29

Applicant: Venkat Raghavan ,  Sheldon Haynie ,  Andrew Strachan

Inventor： Venkat Raghavan ,  Sheldon Haynie ,  Andrew Strachan

IPC: H01L21/20

CPC classification number: H01L23/5223 ,  H01L23/5228 ,  H01L27/016 ,  H01L28/20 ,  H01L28/24 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for integrating a metal-insulator-metal (MIM) capacitor and a thin film resistor in an integrated circuit is provided that includes depositing a first metal layer outwardly of a semiconductor wafer substrate. A portion of the first metal layer forms a bottom plate for a MIM capacitor. A second metal layer is deposited outwardly of the first metal layer. A first portion of the second metal layer forms a top plate for the MIM capacitor and a second portion of the second metal layer forms contact pads for a thin film resistor.

Abstract translation: 提供了一种在集成电路中集成金属 - 绝缘体 - 金属（MIM）电容器和薄膜电阻器的方法，其包括在半导体晶片衬底之外沉积第一金属层。 第一金属层的一部分形成用于MIM电容器的底板。 第二金属层沉积在第一金属层的外部。 第二金属层的第一部分形成用于MIM电容器的顶板，并且第二金属层的第二部分形成用于薄膜电阻器的接触焊盘。

公开(公告)号：US20090254872A1

公开(公告)日：2009-10-08

申请号：US12480916

申请日：2009-06-09

Applicant: Douglas Brisbin ,  Andrew Strachan

Inventor： Douglas Brisbin ,  Andrew Strachan

IPC: G06F17/50

CPC classification number: H01L29/0847 ,  H01L29/7835

Abstract: A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

Abstract translation: 可以根据本发明设计和制造PMOS器件以定位其漏极结击穿点和最大冲击电离点，以减少或消除漏极击穿电压。 在一些实施例中，漏极结击穿点和最大冲击电离点位于距离栅极足够远的位置，器件不会显示出显着的漏极击穿电压。 该器件可以是具有包括P型轻掺杂漏极（P-LDD）注入的扩展漏极区域的高压功率晶体管，漏极结击穿和最大冲击电离点通过控制用于产生P的植入剂量来适当地定位 -LDD植入物。 本发明的其他方面是用于设计PMOS器件的方法，包括通过确定栅极的相对位置和漏极结击穿和最大冲击电离点中的至少一个来减少漏极击穿电压的走向，以及用于制造集成电路的方法，包括 本发明的PMOS器件的任何实施例。

公开(公告)号：US07180140B1

公开(公告)日：2007-02-20

申请号：US10825833

申请日：2004-04-16

Applicant: Douglas Brisbin ,  Andrew Strachan

Inventor： Douglas Brisbin ,  Andrew Strachan

IPC: H01L29/76

CPC classification number: H01L29/0847 ,  H01L29/7835

Abstract: A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

Abstract translation: 可以根据本发明设计和制造PMOS器件以定位其漏极结击穿点和最大冲击电离点，以减少或消除漏极击穿电压。 在一些实施例中，漏极结击穿点和最大冲击电离点位于距离栅极足够远的位置，器件不会显示出显着的漏极击穿电压。 该器件可以是具有包括P型轻掺杂漏极（P-LDD）注入的扩展漏极区的高压功率晶体管，漏极结击穿和最大冲击电离点通过控制用于产生P的植入剂量来适当地定位 -LDD植入物。 本发明的其他方面是用于设计PMOS器件的方法，包括通过确定栅极的相对位置和漏极结击穿和最大冲击电离点中的至少一个来减少漏极击穿电压的走向，以及用于制造集成电路的方法，包括 本发明的PMOS器件的任何实施例。

公开(公告)号：US07067879B1

公开(公告)日：2006-06-27

申请号：US10857152

申请日：2004-05-28

Applicant: Terry Dyer ,  Jim McGinty ,  Andrew Strachan ,  Constantin Bulucea

Inventor： Terry Dyer ,  Jim McGinty ,  Andrew Strachan ,  Constantin Bulucea

IPC: H01L29/72

CPC classification number: H01L29/7813 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

Abstract: The formation of vertical trench DMOS devices can be added to existing integrated BCD process flows in order to improve the efficiency of the BCD devices. The formation of this trench DMOS varies from existing approaches used with discrete trench DMOS devices, in that only two extra mask steps are added to the existing BCD process, instead of the 10 or so mask steps used in existing discrete trench DMOS processes. Further, the location of these additional heat cycles in the BCD process steps can be placed so as to have minimal impact on the other components created in the process. Utilizing an integrated trench device in a BCD process can offer at least a factor-of-two RDS(ON) area advantage over a planar counterpart.

Abstract translation: 垂直沟槽DMOS器件的形成可以添加到现有的集成BCD工艺流程中，以提高BCD器件的效率。 这种沟槽DMOS的形成与使用离散沟槽DMOS器件的现有方法不同，因为在现有的BCD工艺中仅添加了两个额外的掩模步骤，而不是现有离散沟槽DMOS工艺中使用的10个掩模步骤。 此外，BCD工艺步骤中这些额外的热循环的位置可以被放置成对在该过程中产生的其它部件的影响最小。 利用BCD处理中的集成沟槽器件可以提供比平面对等物至少两个因子二的DS（ON）区域优点。

公开(公告)号：US20070264768A1

公开(公告)日：2007-11-15

申请号：US11705975

申请日：2007-02-14

Applicant: Douglas Brisbin ,  Andrew Strachan

Inventor： Douglas Brisbin ,  Andrew Strachan

IPC: H01L21/8238

CPC classification number: H01L29/0847 ,  H01L29/7835

Abstract: A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

Abstract translation: 可以根据本发明设计和制造PMOS器件以定位其漏极结击穿点和最大冲击电离点，以减少或消除漏极击穿电压。 在一些实施例中，漏极结击穿点和最大冲击电离点位于距离栅极足够远的位置，器件不会显示出显着的漏极击穿电压。 该器件可以是具有包括P型轻掺杂漏极（P-LDD）注入的扩展漏极区域的高压功率晶体管，漏极结击穿和最大冲击电离点通过控制用于产生P的植入剂量来适当地定位 -LDD植入物。 本发明的其他方面是用于设计PMOS器件的方法，包括通过确定栅极的相对位置和漏极结击穿和最大冲击电离点中的至少一个来减少漏极击穿电压的走向，以及用于制造集成电路的方法，包括 本发明的PMOS器件的任何实施例。