公开(公告)号：US07420401B2

公开(公告)日：2008-09-02

申请号：US11453324

申请日：2006-06-14

Applicant: Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

Inventor： Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

IPC: H03K3/02

CPC classification number: H03K19/1732 ,  G06F1/22

Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Abstract translation: 集成电路配置有用于指定集成电路内的电路的复位配置向量的引脚。 检测并利用耦合到引脚的低成本外部电阻器的电阻值来识别配置。 集成电路上的逻辑检测并利用电阻值对查找表中的配置向量进行索引。 然后根据索引的配置向量配置集成电路。

公开(公告)号：US20070290731A1

公开(公告)日：2007-12-20

申请号：US11453324

申请日：2006-06-14

Applicant: Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

Inventor： Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

IPC: H03K3/02

CPC classification number: H03K19/1732 ,  G06F1/22

Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Abstract translation: 集成电路配置有用于指定集成电路内的电路的复位配置向量的引脚。 检测并利用耦合到引脚的低成本外部电阻器的电阻值来识别配置。 集成电路上的逻辑检测并利用电阻值对查找表中的配置向量进行索引。 然后根据索引的配置向量配置集成电路。

公开(公告)号：US20070180410A1

公开(公告)日：2007-08-02

申请号：US11342747

申请日：2006-01-30

Applicant: Colin MacDonald ,  John Dalbey ,  Anis Jarrar

Inventor： Colin MacDonald ,  John Dalbey ,  Anis Jarrar

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/62 ,  G06F2217/78

Abstract: A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.

Abstract translation: 一种设计集成电路的方法的系统识别由时钟驱动器驱动的集成电路的多个同步单元，其中多个同步单元是集成电路的先前放置的单元的子集。 执行同步单元的布置以减少从时钟驱动器驱动多个同步单元所需的电流。

公开(公告)号：US06999627B2

公开(公告)日：2006-02-14

申请号：US10025290

申请日：2001-12-19

Applicant: Colin MacDonald ,  Tamas Kovacs

Inventor： Colin MacDonald ,  Tamas Kovacs

IPC: G06K9/36

CPC classification number: G06T9/004 ,  H04N19/42 ,  H04N19/44 ,  H04N19/91

Abstract: Embodiments of the present invention relate to deterministic prediction in an image processing system. One aspect relates to an image processing system having a deterministic prediction decode unit for predicting individual pixels of an image based on a predetermined deterministic prediction algorithm. The deterministic prediction decode unit includes a look-up table, organized into four spatial phases, for storing values to be used by the predetermined deterministic prediction algorithm when converting a relatively low resolution image to a relatively higher resolution image. A prediction is made for a target pixel by accessing at least two of the four spatial phases of the look-up table to read at least two possible values of the target pixel. In one embodiment, the value of two target pixels can be provided within a same clock period, thus allowing for the decoding of two spatial phases with each access to the look-up table.