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    SYSTEMS AND METHODS FOR ELECTRONIC NOTIFICATION QUEUES
    1.
    发明公开
    SYSTEMS AND METHODS FOR ELECTRONIC NOTIFICATION QUEUES 审中-公开

    公开(公告)号：US20240184773A1

    公开(公告)日：2024-06-06

    申请号：US18438813

    申请日：2024-02-12

    申请人： Walmart Apollo, LLC

    发明人： Sandeep Malik ,  Chintan Pankajkumar Shah

    IPC分类号： G06F16/23 ,  G06F1/22 ,  G06F9/54 ,  G06F16/22

    CPC分类号： G06F16/2379 ,  G06F1/22 ,  G06F9/542 ,  G06F9/546 ,  G06F16/22

    摘要： A system can include one or more processors and one or more non-transitory computer-readable media storing computing instructions that, when executed on the one or more processors, cause the one or more processors to perform operations: receiving a new notification; determining, using a binary search algorithm, a number of one or more notifications, wherein an interval of the binary search algorithm comprises a time period between a reclamation pointer and an ingestion pointer; when the number of the one or more notifications is greater than a maximum number of notifications, removing, from a central data store, at least one notification of the one or more notifications; and storing the new notification in the central data store. Other embodiments are described.

    Method and apparatus for multiplexing pins of an integrated circuit
    6.
    发明授权
    Method and apparatus for multiplexing pins of an integrated circuit 有权
    用于复用集成电路引脚的方法和装置

    公开(公告)号：US09252777B2

    公开(公告)日：2016-02-02

    申请号：US14095220

    申请日：2013-12-03

    申请人： Marvell World Trade LTD.

    发明人： Donald Pannell

    IPC分类号： G11C7/00 ,  H03K19/173 ,  G06F1/22 ,  H05B33/08

    CPC分类号： H03K19/1732 ,  G06F1/22 ,  H05B33/0806

    摘要： An integrated circuit within an integrated circuit package, including a configuration module and a timing module. The configuration module configures the integrated circuit using a configure operation performed via N pins of the integrated circuit package, where N is an integer greater than 1. The timing module is configured to control on/off timing of (N*M) light emitting diodes arranged in N columns and M rows connected to the N pins and M pins of the integrated circuit, respectively, where M is an integer greater than 1. During a first period, the configure operation utilizes the N pins. During a second period, the N*M light emitting diodes receive data from the M pins and refresh signals from the N pins. The second period is different than the first period.

    摘要翻译： 集成电路封装内的集成电路，包括配置模块和定时模块。 配置模块使用通过集成电路封装的N个引脚进行的配置操作来配置集成电路，其中N是大于1的整数。定时模块被配置为控制（N * M）个发光二极管的导通/截止定时 分别以N列和M行连接到集成电路的N个引脚和M个引脚，其中M是大于1的整数。在第一个周期期间，配置操作使用N个引脚。 在第二个时间段内，N * M个发光二极管从M个引脚接收数据，并从N个引脚刷新信号。 第二期与第一期不同。

    System and method for detecting states
    8.
    发明授权
    System and method for detecting states 有权
    用于检测状态的系统和方法

    公开(公告)号：US09189658B2

    公开(公告)日：2015-11-17

    申请号：US14248910

    申请日：2014-04-09

    申请人： Nikolai Vyssotski ,  Richard Tonry

    发明人： Nikolai Vyssotski ,  Richard Tonry

    IPC分类号： H04Q5/22 ,  G06K1/00 ,  G06F1/22 ,  H01L21/00

    CPC分类号： G06K1/00 ,  G06F1/22 ,  H01L21/00

    摘要： Systems and methods for detecting states are disclosed. An information handling system may include a processor and a plurality of information handling resources communicatively coupled to the processor via the common control line. The processor may be configured to produce a first signal on a common control line. Each of the plurality of information handling resources may include a tag having a signal threshold, the tag configured to communicate a second signal via the common control line indicating the presence of the particular information handling resource in response to the first signal exceeding the signal threshold of the tag.

    摘要翻译： 公开了用于检测状态的系统和方法。 信息处理系统可以包括经由公共控制线路通信地耦合到处理器的处理器和多个信息处理资源。 处理器可以被配置为在公共控制线上产生第一信号。 多个信息处理资源中的每一个可以包括具有信号阈值的标签，所述标签被配置为响应于超过第一信号的信号阈值而经由公共控制线路传送指示特定信息处理资源的存在的第二信号 标签。

    Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal
    9.
    发明授权
    Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal 有权
    包括读数据选通信号的减少引脚数（RPC）存储器总线接口的装置和方法

    公开(公告)号：US08966151B2

    公开(公告)日：2015-02-24

    申请号：US13435445

    申请日：2012-03-30

    申请人： Clifford Alan Zitlaw

    发明人： Clifford Alan Zitlaw

    IPC分类号： G06F1/08 ,  G06F1/10

    CPC分类号： G06F1/10 ,  G06F1/08 ,  G06F1/22

    摘要： A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device. The interface also includes a differential clock pair for delivering a differential clock signal. A read data strobe is included in the interface for delivering a read data strobe signal from the peripheral device. The interface includes a data bus for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus.

    摘要翻译： 一种用于存储总线接口的方法和装置，包括读数据选通。 该接口包括用于传递芯片选择信号的芯片选择，该芯片选择信号指示外围设备何时被激活，其中所述总线接口提供主机设备和所述外围设备之间的通信。 该接口还包括用于传送差分时钟信号的差分时钟对。 用于从外围设备传送读取数据选通信号的接口中包括读取数据选通脉冲。 该接口包括用于传递命令，地址和数据信息的数据总线。 读数据选通指示当数据总线上存在有效数据时。